Search Jobs | Dice.com

333 results (14 new)

Group by company

Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

Tanisha Systems, Inc.

San Jose, California • 27d ago

Easy Apply

Contract, Third Party

Depends on Experience

ASIC CAD Engineer

Draper

Cambridge, Massachusetts • Today

Full-time

USD 82,300.00 per year

Senior Staff ASIC CAD Flow Infrastructure Engineer

Marvell Semiconductor Inc.

Austin, Texas • Today

Full-time

USD 129,100.00 - 191,030.00 per year

Senior Electrical CAD Engineer

Bayside Solutions

Rockville, Maryland • Today

Easy Apply

Full-time

$77 - $87 per hour

Senior ASIC CAD Engineer

PaloAlto Networks

California • Today

Full-time

USD 173,600.00 - 280,700.00 per year

Senior ASIC RTL DESIGN Engineer

Carlton National Resources, INC

Remote or Hybrid in Boston, Massachusetts • 19d ago

Easy Apply

Contract

90 - 130

Senior ASIC Physical Design Engineer

Johns Hopkins Applied Physics Laboratory (APL)

Laurel, Maryland • Today

Full-time

ASIC Chip Lead / Design Engineer

Technical Link

Brooklyn Park, Minnesota • 6d ago

Easy Apply

Full-time

145,000 - 205,000

Sr. Staff Engineer, ASIC Design

Ayar Labs

San Jose, California • Today

Full-time

USD 180,000.00 - 223,000.00 per year

Senior Engineer, Physical Design Engineering (ASIC)

Analog Devices, Inc.

New Jersey • Today

Full-time

USD 116,960.00 - 160,820.00 per year

DFT MBIST Staff Engineer / Lead ASIC DFT Staff Engineer

ICS Global Soft, Inc.

Remote • Today

Easy Apply

Third Party, Contract

Depends on Experience

Senior ASIC Emulation Engineer

K2 Space

Seattle, Washington • Today

Full-time

USD 170,000.00 - 250,000.00 per year

Senior ASIC Emulation Engineer

K2 Space

Remote • Today

Full-time

USD 170,000.00 - 250,000.00 per year

Lead ASIC DFT Engineer

SAPSOL Technologies Inc.

Remote • Today

Full-time

Remote: Lead ASIC DFT Staff Engineer

J-RAM IT Consulting Inc.

Remote • Today

Easy Apply

Contract

Depends on Experience

Senior Principal ASIC FPGA Engineer

General Dynamics

Remote or Boise, Idaho • Today

Full-time

USD 191,146.00 - 212,053.00 per year

ASIC / FPGA Digital Design Engineer - (Lead or Senior)

Boeing Company

El Segundo, California • Today

Full-time

USD 146,200.00 - 197,800.00 per year

ASIC / FPGA Design Verification Engineer - (Lead or Senior)

Boeing Company

El Segundo, California • Today

Full-time

USD 146,200.00 - 197,800.00 per year

Senior Custom ASIC Engineering Lead

Broadcom Corporation

San Jose, California • Today

Full-time

USD 143,800.00 - 230,000.00 per year

Sr Principal ASIC FPGA Engineer (Sign-on Bonus Available)

General Dynamics

Scottsdale, Arizona • Today

Full-time

USD 182,139.00 - 202,060.00 per year

Senior ASIC Verification Engineer

Cornelis Networks

San Francisco, California • Today

Full-time

Lead ASIC DFT Staff Engineer

Ekcel Technologies Inc

Remote • Today

Easy Apply

Third Party, Contract

Depends on Experience

RTL Engineer, Networking ASIC

InterSources Inc.

Saratoga, California • 5d ago

Easy Apply

Full-time

200000 - 220000

ASIC / FPGA Design Verification Engineer - (Associate or Experienced)

Boeing Company

El Segundo, California • Today

Full-time

USD 98,600.00 - 133,400.00 per year

ASIC / FPGA Digital Design Engineer - (Associate or Experienced)

Boeing Company

El Segundo, California • Today

Full-time

USD 98,600.00 - 133,400.00 per year

ASIC Design Engineer

Infobahn Softworld Inc.

No location provided • Today

Easy Apply

Full-time, Contract, Third Party

ASIC Emulation Engineer

R Cube Creative Consulting Inc

San Jose, California • 27d ago

Easy Apply

Contract

60 - 75

Hardware Engineer (FPGA/ASIC)

Jane Street

New York, New York • Today

Full-time

ASIC Engineer

Jane Street

New York, New York • 29d ago

Full-time

ASIC RTL Design Engineer

Experis

San Jose, California • Today

Full-time

Job Details

Skills

Summary

Hello Professional,

Good Afternoon!!!

Please find the job description give below, if interested please share me your most updated copy of resume.

Role: Lead ASIC DFT Engineer
Work Setup: Remote, PST time zone preferred
Experience Required:

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

Key Pointers

DFT Architecture definition.
Scan & compression(EDT) implementation
LBIST implementation and verification
Coverage improvements (Spyglass work)
ATPG sims - timing & no timing.
Full chip / Sub system level DFT activities.

Key Skills Required:

Strong hands-on ASIC DFT experience with end-to-end ownership
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
MBIST implementation and verification; SMS experience preferred
Tessent/SSN experience preferred
Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
Post-silicon debug and silicon bring-up experience

TCL, PERL, or Python scripting experience is highly preferred

Shivam Maheshwari
Talent Acquisition Manager, Tanisha Systems Inc
ISO Certified Company{ ISO 9001:2015}
Office:
Email:
Address:99 Wood Ave South, Suite # 308, Iselin, NJ 08830

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10117909
Position Id: 26-17500
Posted 27 days ago

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

DFT Engineer Scan / ATPG / MBIST

Santa Clara, California

•

Yesterday

DFT Engineer Scan / ATPG / MBISTLocation: Santa Clara, CA (Bay Area) Position: DFT Engineer Work Arrangement: Onsite/Hybrid as per project requirements Job SummaryWe are seeking a skilled Design for Test (DFT) Engineer to join our semiconductor engineering team in Santa Clara, California. The ideal candidate will have hands-on experience with DFT methodologies, with strong knowledge of Scan, ATPG, and MBIST. The candidate will be responsible for implementing, validating, and debugging DFT solut

Easy Apply

Contract

Depends on Experience

DFT Engineer

San Jose, California

•

Today

Position : DFT Engineer Location : Austin,TX / San Jose,CA Duration : Long-term contract The Role We are seeking highly skilled and motivated Senior/Staff DFT (Design for Test) Engineers with a strong focus on high-performance digital design to take end-to-end ownership of robust, testable silicon, from early test strategy definition to verified DFT implementation, pattern generation, and silicon bring-up. You will join a multidisciplinary group creating next-generation accelerators where digita

Easy Apply

Contract, Third Party

Depends on Experience

DFT Engineer

Santa Clara, California

•

6d ago

Job Title: DFT Engineer Location: Santa Clara, CA Work Arrangement: Onsite Experience: 5+ Years JOB DESCRIPTION We are seeking an experienced DFT Engineer to join a cutting-edge Silicon Engineering team working on next-generation GPU and AI products. The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer to contribute to complex ASIC/SoC designs and next-

Easy Apply

Third Party, Contract

80 - 100

Design For Test Engineer III (IC)

San Jose, California

•

Today

Position:Design For Test Engineer (IC) Job Description:What You\'ll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Sh

Full-time

Job Details

Skills

Summary

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

DFT Architecture definition.
Scan & compression(EDT) implementation
LBIST implementation and verification
Coverage improvements (Spyglass work)
ATPG sims - timing & no timing.
Full chip / Sub system level DFT activities.

Key Skills Required:

Strong hands-on ASIC DFT experience with end-to-end ownership
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
MBIST implementation and verification; SMS experience preferred
Tessent/SSN experience preferred
Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
Post-silicon debug and silicon bring-up experience

TCL, PERL, or Python scripting experience is highly preferred

Shivam Maheshwari
Talent Acquisition Manager, Tanisha Systems Inc
ISO Certified Company{ ISO 9001:2015}
Office:
Email:
Address:99 Wood Ave South, Suite # 308, Iselin, NJ 08830

Dice Id: 10117909
Position Id: 26-17500
Posted 27 days ago

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

DFT Engineer Scan / ATPG / MBIST

Santa Clara, California

•

Yesterday

Easy Apply

Contract

Depends on Experience

DFT Engineer

San Jose, California

•

Today

Easy Apply

Contract, Third Party

Depends on Experience

DFT Engineer

Santa Clara, California

•

6d ago

Easy Apply

Third Party, Contract

80 - 100

Design For Test Engineer III (IC)

San Jose, California

•

Today

Full-time