Physical Design Engineer

Job Title: Physical Design Engineer
Employment Type: Full-Time (FTE)
Locations: San Jose, CA / San Diego, CA / Irvine, CA
Experience: 12+ Years’

Required Technical Skills

· Strong hands-on experience with Cadence Innovus.

· End-to-end Physical Design experience from RTL to tape-out.

· RTL synthesis and Static Timing Analysis (STA).

· Timing closure, including top-level STA.

· Place & Route (P&R), Clock Tree Synthesis (CTS), and clock-tree optimization.

· Floorplanning and physical layout.

· Physical verification and EM/IR analysis.

· Strong TCL and/or PERL scripting skills.

· Experience with industry-standard EDA tools.

· Ability to collaborate with IC Design and RTL Engineering teams.

Key Responsibilities

· Execute physical design, synthesis, physical verification, and timing closure activities.

· Perform RTL setup, synthesis, floorplanning, and Place & Route.

· Develop and optimize clock trees to reduce insertion delay and balance skew.

· Conduct top-level timing analysis and EM/IR analysis.

· Contribute to physical design flow and methodology development.

· Support complex ASIC/SoC designs through tape-out.

Preferred Qualifications

· Deep expertise in top-level floorplanning and STA.

· Proven experience delivering complex ASIC/SoC designs through tape-out.

· Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field.

Recruiter Checkpoints

· · Verify 12+ years of relevant Physical Design experience.

· Confirm strong hands-on Cadence Innovus experience and complete RTL-to-tape-out expertise.

· Prioritize candidates with top-level floorplanning, STA, timing closure, and CTS experience.

· Confirm willingness to work in one of the specified California locations.

· Validate expected salary and availability to join.