Design Verification Engineer

Job Summary

We are seeking a motivated Design Verification Engineer with 1–3 years of experience in digital design verification and semiconductor engineering. The candidate will work with RTL design and verification teams to develop testbenches, execute simulation-based verification, debug design issues, and validate the functionality and reliability of digital designs.

The ideal candidate should have hands-on knowledge of Verilog, SystemVerilog, digital logic design, and verification methodologies such as UVM. Experience with simulation tools, functional coverage, and debugging is highly desirable.

Key Responsibilities

• Develop and maintain verification testbenches using SystemVerilog and UVM.

• Create test plans, test cases, and verification scenarios based on design specifications.

• Perform functional verification of RTL designs through simulation.

• Debug simulation failures and collaborate with RTL designers to resolve functional issues.

• Develop directed and constrained-random tests to validate design behavior.

• Implement and analyze functional coverage and code coverage.

• Write and debug SystemVerilog Assertions (SVA) where applicable.

• Execute regression tests and analyze verification results.

• Document test results, defects, and verification progress.

• Collaborate with design, verification, and validation teams to improve verification quality.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or a related field.

• 1–3 years of experience in Design Verification or a related digital hardware engineering role.

• Strong understanding of digital logic design, combinational and sequential circuits, and finite state machines.

• Hands-on experience with Verilog and SystemVerilog.

• Understanding of UVM and testbench development.

• Familiarity with simulation tools such as QuestaSim, ModelSim, Synopsys VCS, or Cadence Xcelium.

• Knowledge of functional coverage, code coverage, simulation debugging, and regression testing.

• Strong analytical, troubleshooting, and problem-solving skills.

• Ability to work effectively in a collaborative engineering environment.

Preferred Qualifications

• Experience with RTL block, IP, or subsystem verification.

• Knowledge of AMBA protocols such as AXI, AHB, or APB.

• Familiarity with assertion-based verification and constrained-random testing.

• Basic scripting experience in Python, Perl, or Tcl.

• Familiarity with Linux and version control tools such as Git.

• Exposure to semiconductor design and verification workflows.