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Analog Layout Engineer

Inabia Software & Consulting Inc.

Remote • 5d ago

Easy Apply

Contract, Third Party

Depends on Experience

Analog Layout Engineer (eInfochips)

Arrow Electronics, Inc.

Remote or Texas • Today

Full-time

Freelance Layout Designer (Remote)

Workada

Columbus, Ohio • Today

Full-time

Compensation information provided in the description

Contract Layout Designer (Remote)

Workada

Columbus, Ohio • Today

Full-time

Compensation information provided in the description

Junior Layout Designer (Remote)

Workada

Columbus, Ohio • Today

Full-time

Compensation information provided in the description

Staff Engineer, PCB Layout

Celestica International LP

Remote • Today

Full-time

USD 150,000.00 - 240,000.00 per year

Factory Layout Optimization SME

IT FACE Inc.

Remote • 7d ago

Easy Apply

Contract, Third Party

Depends on Experience

Layout Field Engineer

Lithko Contracting LLC

Columbus, Ohio • Today

Full-time

Job Details

Skills

Antennas
CMOS
Information Retrieval
ESD
Investor Relations
Layout
Mixed-signal Integrated Circuit
Internal Communications
International Relations
LVS
SERDES
Integrated Circuit
Analog Layout Engineer
Design Rule Check

Summary

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design
Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]
Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection
Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)
Experience at Lower node (N3, N5) is critical for this position.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10337997
Position Id: 9133710
Posted 5 days ago

Fitment

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Adhunika Sharma

Recruiter @ Inabia Software & Consulting Inc.

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Remote jobs at Inabia Software & Consulting Inc.

Job Details

Skills

Antennas
CMOS
Information Retrieval
ESD
Investor Relations
Layout
Mixed-signal Integrated Circuit
Internal Communications
International Relations
LVS
SERDES
Integrated Circuit
Analog Layout Engineer
Design Rule Check

Summary

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design
Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]
Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection
Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)
Experience at Lower node (N3, N5) is critical for this position.

Dice Id: 10337997
Position Id: 9133710
Posted 5 days ago

Fitment