Physical Design Engineer
Contract Independent
12 Months
No Travel Required
Remote
$100 - $110/hr
Fitment
Dice Job Match Score™
🔢 Crunching numbers...
Job Details
Skills
- ASIC
- ARM
- Design Review
- Digital Circuit Design
- Electrical Engineering
- Integrated Circuit
- PASS
- SERDES
- Signal Integrity
- SystemVerilog
- Static Timing Analysis
- System On A Chip
- Verilog
- Fusion
- RTL
- Synopsys
- Siemens
- Physical Data Model
Summary
Physical Design (Place & Route) Engineer
Fully remote
Fully remote
Duration: Long term contract
About the Role
Our ASIC team is hiring a seasoned Place and Route (P&R) Engineer to own the physical implementation of complex, high-performance chips. You will take designs from a synthesized netlist all the way to final GDSII, pushing hard on power, performance and area (PPA) while protecting design integrity, manufacturability and the schedule.
What You’ll Do
- Run full-chip physical implementation from netlist to GDSII, covering floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization and timing closure.
- Use Synopsys Fusion Compiler for implementation, optimization and closure.
- Handle physical verification and signoff in Siemens Calibre (DRC and LVS), and fix the violations that come up.
- Tune designs to hit PPA goals while meeting timing, signal integrity, reliability and manufacturability requirements.
- Build floorplans around complex IP and high-speed interfaces such as DDR and SerDes.
- Support implementation and integration of RISC-V processor-based designs and subsystems, including timing, power and physical considerations.
- Perform static timing analysis and drive closure across operating modes, process corners and constraint sets.
- Find and resolve congestion, routing, timing, power integrity and physical verification issues throughout the flow.
- Work closely with RTL design, verification, DFT, analog/mixed-signal, packaging and other teams to make chip integration succeed.
- Integrate and implement third-party and in-house IP blocks.
- Join design reviews and advise on floorplanning, physical architecture, implementation strategy and PPA tradeoffs.
- Develop and improve physical design flows, scripts, methodologies and automation to raise efficiency and quality.
- Troubleshoot hard implementation and signoff problems and drive fixes to completion.
- Support final signoff and tapeout, confirming all physical design and verification requirements are met.
- Coach and mentor other engineers and help grow the team’s physical design capabilities.
What You Bring
- Bachelor’s or master’s degree in electrical engineering, computer science or an equivalent field.
- 10+ years of hands-on industry experience in ASIC and/or SoC design.
- Proficiency with Synopsys Design Compiler and other EDA tools.
- Solid grounding in digital design principles.
- Familiarity with RISC architectures such as ARM and MIPS.
- Strong background in RTL-based digital IC design using Verilog/SystemVerilog.
- A record of first-pass silicon success.
- A self-starting attitude and the ability to step into leadership roles.
- Comfort working in a diverse team, and a willingness to mentor less experienced engineers.
- Experience with industry-standard development tools and methodologies
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
- Dice Id: 91174723
- Position Id: 9136226
- Posted 3 hours ago
Create job alert
Never miss an opportunity! Create an alert based on the job you applied for.