Analog Layout Engineer

Remote • Posted 9 hours ago • Updated 9 hours ago
Contract Independent
Contract W2
Contract Corp To Corp
12 Months
No Travel Required
Remote
Depends on Experience
Fitment

Dice Job Match Score™

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Job Details

Skills

  • Antennas
  • CMOS
  • Information Retrieval
  • ESD
  • Investor Relations
  • Layout
  • Mixed-signal Integrated Circuit
  • Internal Communications
  • International Relations
  • LVS
  • SERDES
  • Integrated Circuit
  • Analog Layout Engineer
  • Design Rule Check

Summary

High-Speed Analog Layout Engineer designs the physical silicon layout for high-frequency or high-speed mixed-signal circuits (such as SerDes, ADCs, DACs, PLLs, and High speed blocks).

  • Floor Planning & Integration: Create block-level and chip-top-level floor plans, manage hierarchical block integration, and handle micro-bump or package-aware co-design
  • Parasitic & Noise Control: Address layout-dependent effects (LOD, WPE, LDE), device matching, common-centroid structures, guard rings, and isolation or shielding (coaxial, differential, ground shields). [1, 2, 3]
  • Reliability & Verification: Ensure complete closure on DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC, antenna rules, EM/IR (Electromigration / Infrared drop) reliability, and ESD protection
  • Generally 5 to 12+ years of hands-on custom IC layout experience in deep sub-micron or advanced CMOS/FinFET nodes (such as TSMC N3, N5, N7)
  • Experience at Lower node (N3, N5) is critical for this position.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10337997
  • Position Id: 9133710
  • Posted 9 hours ago
Contact the job poster
AS

Adhunika Sharma

Recruiter @ Inabia Software & Consulting Inc.

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