Job Details
ASIC Design Verification Engineer
12+ Months Contract with Possible Extension
Austin, TX & Menlo park, CA
Job Summary
We are seeking a highly motivated ASIC Design Verification Engineer to join our silicon engineering team. The ideal candidate will have strong experience in SystemVerilog/UVM-based verification of complex IPs or SoCs and will be responsible for developing test cases, debugging RTL issues, and driving coverage closure.
Responsibilities
Maintain reusable SystemVerilog/UVM verification environments.
Develop directed and constrained-random test cases to verify functionality and corner cases.
Perform regression debugging and root-cause analysis of RTL and testbench failures.
Drive functional and code coverage closure to meet project milestones.
Collaborate closely with RTL designers to resolve the design issues.
Required Qualifications
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
5+ years of experience in ASIC/SoC Design Verification.
Strong expertise in SystemVerilog and UVM.
Experience with constrained-random verification and coverage-driven methodologies.
Strong debugging skills using waveform and simulation tools.
Experience developing assertions (SVA) and functional coverage.
Familiarity with version control systems and Linux development environments.
Preferred Qualifications
Experience verifying one or more of the following:
PCIe (Gen4/Gen5/Gen6)
Ethernet (100G/200G/400G/800G)
AXI4 / AHB / APB
DMA
HBM/DDR memory subsystems
NoC / Interconnect fabrics
RDMA / RoCE
Cache-coherent protocols.
Required Skills
SystemVerilog
UVM
Functional Coverage
Assertions (SVA)
Verification Planning
RTL Debug
Regression Debug
Protocol Verification
