Position 1
Physical Design Engineer
Mountain View CA (onsite - Hybrid)
Mode of hiring: Fulltime permanent
Customer wants someone who is having some logical design experience along with PD experience.
Having some RTL2PD flow skills such as CDC/RDC/VCLP is preferred.
Having some exposure of logic design is also preferred. Canddiate doesn't have to do the logic design, but needs to review the synthesis/PNR report to analyze for the timing/LoL optimization
Provides services in transforming the RTL design into a physical layout of the chip using Synopsys Fusion Compiler synthesis and place-and-route tools. The physical design process involves specifying various constraints on the netlist, such as timing, power, area and design rules, and optimizing the layout for performance, quality, and reliability, especially in the latest nodes such as 5nm and 3nm.
- RTL to GDSII:
Synthesis, Placement and Routing using Fusion Compiler
Block and SOC Floor planning using Fusion Compiler
Clock Tree Synthesis - Signoff checks:
Timing using Primetime
Extraction using Star RC
EMIR closure using Redhawk-SC - ECO implementation:
Logical ECOs using Formality ECO
Timing ECOs using Prime Closure
Having some RTL2PD flow skills such as CDC/RDC/VCLP is preferred.
Having some exposure of logic design is also preferred. Candidate doesn't have to do the logic design, but needs to review the synthesis/PNR report to analyze for the timing/LoL optimization.
Position 2
Physical Design Engineer (PnR / PPA / Timing Closure)
Austin/TX
Open for both fulltime and contracts
Job Description
We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.
Key Responsibilities
Drive block-level physical design implementation from netlist to GDSII.
Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
Optimize designs for Power, Performance, and Area (PPA) targets.
Achieve timing closure across multiple corners and modes.
Analyze and resolve setup, hold, transition, capacitance, and noise violations.
Develop and maintain timing constraints (SDC) and STA signoff methodologies.
Perform EMIR (Electromigration & IR Drop) analysis and closure.
Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
Debug physical design issues and drive design convergence within project schedules.
Required Skills
Strong experience in Physical Design and PnR flow.
Hands-on expertise in:
o Floorplanning
o Placement & Optimization
o Clock Tree Synthesis (CTS)
o Routing
o Timing Closure
o Static Timing Analysis (STA)
o Timing Constraints (SDC)
o EMIR Analysis
o PPA Optimization
Experience with industry-standard EDA tools such as:
o Synopsys Fusion Compiler / ICC2
o PrimeTime
o Cadence Innovus (optional)
o RedHawk / Voltus (EMIR)
Good understanding of low-power design techniques and signoff methodologies.
Preferred Qualifications
Bachelor's or Master's degree in Electrical/Electronics Engineering.
Experience in advanced nodes (7nm/5nm/3nm preferred).
Strong debugging and problem-solving skills.
Experience working with cross-functional silicon teams
