Design Verification Engineer – UVM/SystemVerilog

Job Summary

We are seeking an experienced Design Verification (DV) Engineer to join our Interface IP Design Verification team. The ideal candidate will have strong hands-on experience in SystemVerilog and UVM-based verification, along with expertise in validating complex IP subsystems and standard interface protocols. You will collaborate closely with architects, RTL designers, integration teams, and external IP vendors to ensure functional correctness, performance, and compliance with architectural specifications across the hardware-software stack.

Key Responsibilities

• Own end-to-end design verification for one or more IP subsystems, including PCIe, Ethernet, ARM/ARC CPUs, low-power peripherals, and sensors.

• Develop, maintain, and enhance reusable verification environments using SystemVerilog and UVM.

• Understand vendor IP configurations, specifications, and integration requirements while coordinating with internal IP teams and external vendors.

• Verify functional correctness, performance, protocol compliance, and corner-case scenarios.

• Collaborate with SoC Design Verification and integration teams to ensure seamless integration of third-party IPs into the overall chip architecture.

• Develop and execute verification plans, test scenarios, and regression suites.

• Drive functional and code coverage closure, analyze verification gaps, and support final verification sign-off.

• Debug complex failures, identify root causes, and work closely with RTL design and software teams to resolve issues.

• Communicate verification progress, technical findings, risks, and recommendations to cross-functional stakeholders.

Required Qualifications

• 5+ years of hands-on experience in Design Verification Engineering.

• Strong proficiency in SystemVerilog and UVM methodologies.

• Experience developing scalable, reusable testbenches and constrained-random verification environments.

• Familiarity with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, and ARM/ARC CPUs.

• Experience with functional coverage, coverage analysis, regression testing, and verification sign-off.

• Strong debugging, problem-solving, and analytical skills.

• Ability to work independently, take ownership of verification tasks, and deliver results with minimal supervision.

• Excellent communication and collaboration skills when working with design, architecture, integration, and software teams.

Preferred Qualifications

• Experience working with external IP vendors and managing IP/VIP integration.

• Hands-on experience with UVM-based verification and SystemVerilog testbench development.

• Knowledge of SoC integration and hardware-software interaction.

• Experience identifying corner-case bugs and debugging complex IP-level issues.

• Ability to thrive in a fast-paced engineering environment and manage multiple verification priorities.