We are looking for an experienced RTL Verification Engineer with strong expertise in DFX (Design for X), VISA/Debug, JTAG, and ASIC/SoC verification. The ideal candidate will have hands-on experience developing and executing verification environments for debug logic, DFX features, scan/debug interfaces, and related RTL.
DFX – RTL Verification Engineer | VISA / JTAG / Debug Validation
Location: Santa Clara, CA
Duration: 12 Months
Key Responsibilities & Requirements
- 6 – 8 years of hands-on experience in RTL Design Verification, DFX Verification, or ASIC/SoC Verification.
- Strong experience in DFX (Design for X) verification and validation of DFX-related RTL.
- Hands-on experience with JTAG / IEEE 1149.x architecture, TAP controllers, and boundary-scan concepts.
- Strong knowledge of VISA (Vendor Independent Silicon Architecture) / VISA Debug and related validation methodologies.
- Experience validating debug logic, debug access mechanisms, scan/debug interfaces, and associated RTL.
- Strong hands-on expertise in SystemVerilog and UVM.
- Experience developing and maintaining UVM testbenches, test scenarios, assertions, functional coverage, and verification plans.
- Hands-on experience with simulation, waveform/debug analysis, failure investigation, and root-cause analysis.
- Experience working within complex ASIC/SoC verification environments.
- Good understanding of DFT/DFX concepts, scan architectures, TAP controllers, JTAG, and boundary scan.
- Strong scripting/programming skills using Python, Perl, Tcl, or similar languages.
- Experience with industry-standard verification and debug tools such as Synopsys VCS/Verdi, Siemens Questa/ModelSim, or equivalent is preferred.
Ideal Candidate
The ideal candidate should be able to independently drive DFX/VISA/JTAG verification activities, develop robust SystemVerilog/UVM-based verification environments, debug complex RTL failures, and work closely with Design, DFT, Architecture, and Silicon Validation teams.
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