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Principal AI Forward Deployment Engineer

Cadence Design Systems Inc

Oregon • Today

Full-time

Principal Forward Deployed AI Engineer

EPAM Systems

Remote • Today

Full-time

Principal Forward Deployed Engineer - Agentic AI

OutSystems

Remote or Boston, Massachusetts • Today

Full-time

USD 153,000.00 - 186,300.00 per year

Principal Forward Deployed Engineer

Atlassian Inc.

Remote or Seattle, Washington • Today

Full-time

USD 209,700.00 - 273,775.00 per year

Senior Principal Forward Deployed Engineer

Atlassian Inc.

Remote or Seattle, Washington • Today

Full-time

USD 243,900.00 - 318,425.00 per year

Staff Forward Deployed Engineer, AI

SentinelOne

Remote • Today

Full-time

USD 156,000.00 - 215,000.00 per year

Staff Forward Deployed AI Solutions Engineer

Natera, Inc.

Remote • Today

Full-time

USD 152,100.00 - 190,100.00 per year

Senior Staff Forward Deployed Engineer, AI

SentinelOne

Remote • Today

Full-time

USD 184,000.00 - 253,000.00 per year

Principal Engineer, AI

Anaplan

Remote or Pennsylvania • Today

Full-time

Principal Engineer - AI Platform

iHerb inc

Remote • 10d ago

Full-time

USD 204,000.00 - 260,000.00 per year

Principal AI Platform Engineer

Datasite

Remote • Today

Full-time

USD 117,500.00 - 206,700.00 per year

Principal AI-Driven Enterprise Support Engineer

NICE Systems

Remote • Today

Full-time

AI Accelerator Software Principal Engineer- Framework Integration

Ampere Computing LLC

Portland, Oregon • Today

Full-time

USD 182,000.00 - 273,000.00 per year

Principal AI Engineer

Cotiviti

Remote • Today

Full-time

USD 208,000.00 - 260,000.00 per year

Principal AI Platform Engineer

Lynx Software Technologies

Remote • Today

Full-time

USD 190,000.00 - 225,000.00 per year

Principal ML/AI Engineer

White Cap Supply Holdings, LLC

Remote • Today

Full-time

Principal AI/ML Research Engineer

WEX Inc

Remote • Today

Full-time

USD 250,300.00 - 289,000.00 per year

Principal AI Solutions Engineer

Bausch & Lomb

Remote or California • Today

Full-time

USD 165,000.00 - 190,000.00 per year

Principal Engineer - AI Security

Thrivent Financial for Lutherans

Remote or Minnesota • Today

Full-time

USD 161,436.00 - 218,415.00 per year

AI Principal Engineer

WEX Inc

Remote • Today

Full-time

USD 250,300.00 - 289,000.00 per year

Principal AI Engineering Architect

Robots and Pencils

Remote • Today

Full-time

USD 180,375.00 - 230,625.00 per year

Principal AI Engineering Consultant

Acunor Infotech

Remote or California • Today

Easy Apply

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$$160000 - 200000 per year

Principal AI Engineering Architect

SentinelOne

Remote • Today

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USD 224,000.00 - 308,000.00 per year

Staff Forward Deployed Engineer

Hims and Hers Health, Inc.

Remote • Today

Full-time

USD 195,000.00 - 240,000.00 per year

Staff Forward Deployed Engineer

JLL

Remote or Chicago, Illinois • Today

Full-time

USD 150,000.00 - 280,000.00 per year

Principal Engineer

Atlassian Inc.

Remote or Seattle, Washington • Today

Full-time

USD 209,700.00 - 273,775.00 per year

Staff Forward Deployed Engineer

GitLab

Remote • Today

Full-time

USD 254,000.00 - 297,000.00 per year

Applied AI Staff Engineer

TalTeam

Remote • 5d ago

Easy Apply

Contract

Depends on Experience

Staff Machine Learning Engineer, Applied Research

Pinterest, Inc.

Remote or San Francisco, California • Today

Full-time

USD 189,308.00 - 389,753.00 per year

Principal Software Engineer (Libraries Platform)

Chainguard

Remote • Today

Full-time

USD 229,000.00 - 258,000.00 per year

Job Details

Skills

Recruiting
WINS
Allegro
Embedded Systems
Place And Route
Productivity
Return On Investment
Reporting
KPI
PASS
Design Review
Roadmaps
Research and Development
Information Security
Capacity Management
Mentorship
Semiconductors
Integrated Circuit
DV
Physical Data Model
IT Management
Fluency
Debugging
Communication
RTL
Pure Data
Shipping
Customer Facing
Cadence
Synopsys
Siemens
Autogen
Microsoft Certified Professional
Stacks Blockchain
Access Gateways
Routing
Management
Auditing
GPU
Workflow
Evaluation
Machine Learning (ML)
Computer Networking
HPC
Operations Support Systems
Artificial Intelligence
Data Analysis
EDA

Recruiting
WINS
Allegro
Embedded Systems
Place And Route
Productivity
Return On Investment
Reporting
KPI
PASS
Design Review
Roadmaps
Research and Development
Information Security
Capacity Management
Mentorship
Semiconductors
Integrated Circuit
DV
Physical Data Model
IT Management
Fluency
Debugging
Communication
RTL
Pure Data
Shipping
Customer Facing
Cadence
Synopsys
Siemens
Autogen
Microsoft Certified Professional
Stacks Blockchain
Access Gateways
Routing
Management
Auditing
GPU
Workflow
Evaluation
Machine Learning (ML)
Computer Networking
HPC
Operations Support Systems
Artificial Intelligence
Data Analysis
EDA

Summary

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role Summary

Cadence is hiring a Principal AI Forward Deployment Engineer to embed with strategic semiconductor customers and operationalize Cadence's AI and agentic solutions across their end-to-end silicon design flows. This is a senior, customer-facing applied-AI role for an experienced chip-design practitioner who can translate front-end, physical-design, and methodology workflows into concrete, measurable productivity wins powered by flagship LLMs and Cadence AI tooling. You will be the trusted technical lead at the customer who turns 'AI for chip design' from a slideware promise into a deployed, adopted, and ROI-positive reality.

Why This Role Exists

Customers are racing to apply LLMs and agentic AI to RTL, verification, implementation, and signoff - but they need a partner who deeply understands *both* their tape-out flows and how to wield modern AI systems.
This role owns the last mile: taking Cadence AI products (AgentStack, BU Super-Agents, Cadence.AI / JEDAI platform, Cerebrus, Verisium, Allegro X AI, etc.) and making them work inside the customer's actual methodology, PDKs, compute fabric, and security boundaries.
Success here directly accelerates customer tape-outs, expands Cadence AI footprint, and feeds product roadmaps with real-world signal.

What You Will Do

Customer-Embedded Deployment. Lead end-to-end deployment of Cadence AI / LLM-powered solutions into the customer's silicon design flows - from RTL design and verification through synthesis, place-and-route, timing, power, signoff, and packaging.
Applied AI for Chip Design. Architect and tune agentic workflows, prompt strategies, RAG pipelines, and tool-calling patterns on top of flagship LLMs (Claude, GPT, Gemini, Llama, Qwen, etc.) to automate real EDA tasks - debug triage, constraint authoring, ECO loops, PD recipe tuning, methodology Q&A, log/report summarization, and design-review copilots.
Methodology & Flow Integration. Map customer methodology (FE design, DV, PD, CAD, signoff) onto Cadence AI building blocks; identify the highest-ROI insertion points; build reference flows the customer's CAD/methodology team can own long-term.
Productivity & ROI Ownership. Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass success, license/compute efficiency. Own the story from pilot to production rollout across BUs and sites.
Trusted Technical Advisor. Be the senior technical face to customer fellows, methodology leads, and design-team principals. Run design reviews, technical readouts, and joint roadmaps. Translate customer pain into actionable feedback for Cadence R&D and AI platform teams.
AI Systems Enablement (plus). Where needed, guide customer IT/InfoSec on secure LLM access patterns, on-prem vs. gateway deployment, model routing, prompt/response logging, data-egress controls, and GPU/inference capacity planning.
Knowledge Multiplier. Capture playbooks, reference designs, and 'golden prompts' so every deployment compounds. Mentor field AEs, FAEs, and customer champions.

Must-Have Qualifications

BS/MS/PhD in EE, ECE, CS, or related discipline.
10+ years of hands-on semiconductor / chip design experience in one or more of: front-end design (RTL, micro-architecture, DV), physical design / implementation (synthesis, P&R, timing, power, signoff), CAD / methodology / flow development, or design execution / project technical leadership on production tape-outs.
Deep, practitioner-level fluency with industry EDA flows and pain points - you have personally shipped silicon and know where the cycle-time and engineer-time really go.
Demonstrated ability to apply LLMs / AI tools to get real engineering work done (e.g., agent-based debug, code/RTL generation assist, scripted automation, copilots, RAG over design docs/logs). Doesn't have to be your title - has to be your reflex.
Excellent customer-facing communication: equally credible with a staff RTL engineer, a PD methodology lead, and a CAD / design-enablement leader.
Bias to action, ownership, and shipping. Comfortable being the single throat-to-choke for a customer-facing AI deployment.
Based in or willing to relocate to Portland, OR; able to be on-site at customer locations as the engagement requires.

Nice-to-Have / Bonus

Prior experience as a Cadence / Synopsys / Siemens EDA customer power user, AE, or methodology architect.
Hands-on with at least one agentic framework (Claude Code, Cursor, LangGraph, AutoGen, custom MCP/tool-calling stacks) applied to engineering workflows.
Experience standing up secure enterprise LLM access (gateways, model routing, key management, audit logging) for engineering orgs.
Familiarity with GPU/inference infrastructure, vLLM/TGI/Triton, fine-tuning / LoRA / SLM workflows, and evaluation harnesses for code/EDA tasks.
Background in low-power, high-performance, AI/ML, networking, automotive, or HPC silicon programs.
Public artifacts - papers, talks, OSS, or internal champions - showing applied AI in EDA/silicon contexts.

We're doing work that matters. Help us solve what others can't.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: CADENCE
Position Id: 90b8f966848981f0f12cd997621e2d7f
Posted 30+ days ago

Fitment

Dice Job Match Score™

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Job Details

Skills

Recruiting
WINS
Allegro
Embedded Systems
Place And Route
Productivity
Return On Investment
Reporting
KPI
PASS
Design Review
Roadmaps
Research and Development
Information Security
Capacity Management
Mentorship
Semiconductors
Integrated Circuit
DV
Physical Data Model
IT Management
Fluency
Debugging
Communication
RTL
Pure Data
Shipping
Customer Facing
Cadence
Synopsys
Siemens
Autogen
Microsoft Certified Professional
Stacks Blockchain
Access Gateways
Routing
Management
Auditing
GPU
Workflow
Evaluation
Machine Learning (ML)
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HPC
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EDA

Recruiting
WINS
Allegro
Embedded Systems
Place And Route
Productivity
Return On Investment
Reporting
KPI
PASS
Design Review
Roadmaps
Research and Development
Information Security
Capacity Management
Mentorship
Semiconductors
Integrated Circuit
DV
Physical Data Model
IT Management
Fluency
Debugging
Communication
RTL
Pure Data
Shipping
Customer Facing
Cadence
Synopsys
Siemens
Autogen
Microsoft Certified Professional
Stacks Blockchain
Access Gateways
Routing
Management
Auditing
GPU
Workflow
Evaluation
Machine Learning (ML)
Computer Networking
HPC
Operations Support Systems
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Data Analysis
EDA

Summary

Customers are racing to apply LLMs and agentic AI to RTL, verification, implementation, and signoff - but they need a partner who deeply understands *both* their tape-out flows and how to wield modern AI systems.
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What You Will Do

Customer-Embedded Deployment. Lead end-to-end deployment of Cadence AI / LLM-powered solutions into the customer's silicon design flows - from RTL design and verification through synthesis, place-and-route, timing, power, signoff, and packaging.
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Methodology & Flow Integration. Map customer methodology (FE design, DV, PD, CAD, signoff) onto Cadence AI building blocks; identify the highest-ROI insertion points; build reference flows the customer's CAD/methodology team can own long-term.
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Knowledge Multiplier. Capture playbooks, reference designs, and 'golden prompts' so every deployment compounds. Mentor field AEs, FAEs, and customer champions.

Must-Have Qualifications

BS/MS/PhD in EE, ECE, CS, or related discipline.
10+ years of hands-on semiconductor / chip design experience in one or more of: front-end design (RTL, micro-architecture, DV), physical design / implementation (synthesis, P&R, timing, power, signoff), CAD / methodology / flow development, or design execution / project technical leadership on production tape-outs.
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Excellent customer-facing communication: equally credible with a staff RTL engineer, a PD methodology lead, and a CAD / design-enablement leader.
Bias to action, ownership, and shipping. Comfortable being the single throat-to-choke for a customer-facing AI deployment.
Based in or willing to relocate to Portland, OR; able to be on-site at customer locations as the engagement requires.

Nice-to-Have / Bonus

Prior experience as a Cadence / Synopsys / Siemens EDA customer power user, AE, or methodology architect.
Hands-on with at least one agentic framework (Claude Code, Cursor, LangGraph, AutoGen, custom MCP/tool-calling stacks) applied to engineering workflows.
Experience standing up secure enterprise LLM access (gateways, model routing, key management, audit logging) for engineering orgs.
Familiarity with GPU/inference infrastructure, vLLM/TGI/Triton, fine-tuning / LoRA / SLM workflows, and evaluation harnesses for code/EDA tasks.
Background in low-power, high-performance, AI/ML, networking, automotive, or HPC silicon programs.
Public artifacts - papers, talks, OSS, or internal champions - showing applied AI in EDA/silicon contexts.

We're doing work that matters. Help us solve what others can't.

Dice Id: CADENCE
Position Id: 90b8f966848981f0f12cd997621e2d7f
Posted 30+ days ago

Fitment

Dice Job Match Score™

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Similar Jobs

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