Job Title: DFT / MBIST Engineer — 100% Remote
Location: Remote within the United States
Working Hours: Must align with Pacific Time
Employment Type: W2 / C2C
Experience: Senior engineers preferred; junior candidates with relevant DFT, BIST, or verification experience will also be considered.
Position Overview
TechAGI Solutions is seeking a DFT / MBIST Engineer to support a semiconductor client’s SoC Design-for-Test team. The position focuses on Memory Built-In Self-Test implementation, integration, verification, simulation, pattern generation, and debug.
Senior candidates should be capable of independently owning the complete MBIST flow using Synopsys SMS, VCS, and VecGen. Junior candidates should demonstrate strong RTL, testing, and verification fundamentals through industry experience, internships, or academic projects.
Key Responsibilities
Perform or support MBIST insertion for complex SoC designs using Synopsys SMS.
Integrate and verify MBIST controllers and memory-test infrastructure at block and top levels.
Develop, execute, and debug RTL, no-delay gate-level, and timing-aware simulations using Synopsys VCS.
Generate and validate MBIST test patterns using VecGen.
Troubleshoot RTL, memory-test integration, simulation, clock/reset sequencing, and test-control issues.
Support memory-test algorithms, diagnostics, and repair verification.
Assist with silicon bring-up, characterization, and post-silicon memory failure analysis.
Collaborate with DFT, RTL, verification, Physical Design, and Product Engineering teams.
Develop scripts to automate implementation, verification, reporting, and debug.
Document implementation flows, test results, and root-cause findings.
Qualifications — Experienced Candidates
Hands-on DFT experience with a significant focus on MBIST.
Experience with Synopsys SMS, preferably SMS5 and/or SMS6.
Proficiency with Synopsys VCS and VecGen.
Experience across MBIST insertion, integration, verification, pattern generation, diagnostics, and debug.
Knowledge of March algorithms and memory repair schemes, including BIRA/BISR, redundancy analysis, and spare row/column allocation.
Experience debugging no-delay and timing-aware simulations.
Silicon bring-up and post-silicon memory failure analysis experience.
Ability to work independently with minimal supervision.
Qualifications — Junior Candidates
Relevant DFT, BIST, RTL design, or verification experience through employment, internships, or academic projects.
Working knowledge of Verilog/SystemVerilog, simulation, and digital design fundamentals.
Understanding of test-pattern generation, fault models, and memory-testing concepts.
Familiarity with synthesis, static timing analysis, or gate-level simulation.
Willingness to develop hands-on expertise in Synopsys SMS, VCS, and VecGen.
Preferred Skills
Complex SoC designs containing multiple memory instances.
Scan insertion, ATPG, and hierarchical DFT integration.
Tcl, Perl, or Python scripting.
Strong debugging, communication, and documentation skills.
How to Apply
Apply with your updated resume highlighting relevant MBIST/DFT projects, tools used, and your individual contributions and mail to
Skills: DFT, MBIST, Memory BIST, Synopsys SMS, SMS5, SMS6, Synopsys VCS, VecGen, MBIST Insertion, MBIST Integration, MBIST Verification, Memory Diagnostics, March Algorithms, BIRA, BISR, Memory Repair, RTL Verification, Gate-Level Simulation, SDF, Timing Simulation, Silicon Bring-Up, Post-Silicon Debug, SoC, ASIC, Verilog, SystemVerilog, ATPG, Scan Insertion, Tcl, Perl, Python
