Role : Principal Networking Architect, Ethernet Switch Silicon
Location : Remote (PST)
Type : Contract / Full-Time
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Experience
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15+ years in networking silicon, 8+ years in architecture roles
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You will define the architecture of high-radix Ethernet switch ASICs, covering the packet processing pipeline, buffering and traffic management, and the MAC/PCS/SerDes port subsystem. Target markets include data center, AI/ML cluster fabrics, and enterprise and carrier networks.
You will turn customer and market requirements into architecture specs, performance models and PPA trade-offs. You will then guide RTL, verification, physical design and software teams through tapeout and silicon bring-up.
About Client: Client Solutions, a Client company, is a semiconductor engineering partner that delivers chip design from architecture through silicon for customers worldwide.
Key responsibilities
You own the switch architecture end to end and are accountable for it meeting its throughput, latency, power and area targets in silicon.
- Switch architecture: Define the top-level architecture for 12.8T to 102.4T class Ethernet switch ASICs, including port mix (10G to 800G/1.6T), radix, pipeline count and die or chiplet partitioning.
- Packet processing: Architect ingress and egress parsing, L2/L3 forwarding, tunneling (VXLAN, Geneve, MPLS, SRv6), ACLs, and table lookups (TCAM, LPM, exact match, hashing and ECMP). Define programmable pipeline features where needed.
- Traffic management: Design the shared-buffer architecture, queuing, scheduling (strict priority, DWRR), shaping and policing. Own congestion management, including ECN, PFC, lossless Ethernet and cut-through latency.
- AI/HPC fabrics: Define features for AI back-end networks: adaptive routing, packet spraying, RoCEv2 support, Ultra Ethernet (UEC) capabilities, grained telemetry.
- Port subsystem: Specify the MAC, PCS and FEC per IEEE 802.3, integration of 112G/224G SerDes, link training IEEE 1588 PTP and SyncE timing, and MACsec.
- Memory and chip infrastructure: Size on-chip SRAM and TCAM define the internal crossbar or fabric.
- Specs and execution: Write architecture and micro-architecture specs. Guide RTL, DV, DFT, physical design and SDK teams. Support emulation, FPGA prototyping and post-silicon bring-up and debug.
- Software interface: Define the programming model, SAI/SDK hooks and telemetry interfaces, and work with SONiC and NOS teams.
- Customers: Lead technical discussions with customers, translate their requirements into specs, and support proposals, estimates and statements of work.
- Leadership: Mentor architects and designers and help build Client's networking architecture practice.
Required qualifications
The must-have is a production track record: you have architected Ethernet switch silicon that shipped.
- BS, MS or PhD in Electrical Engineering, Computer Engineering or Computer Science.
- 15+ years in networking ASIC or SoC development, with 8+ years in architecture roles.
- Architected at least one Ethernet switch ASIC (or switch/router NPU) that reached volume production. You can name the chip, your scope and the result.
- Deep knowledge of L2/L3 switching and routing, packet parsing and forwarding pipelines, and TCAM, LPM and hash-based lookups.
- Hands-on design of buffering, queuing, scheduling and congestion control in high-bandwidth switches.
- Strong command of IEEE 802.3 (MAC, PCS, FEC), IEEE 802.1 (VLANs, QoS, PFC/DCB) and RoCEv2.
- Experience building performance models in C, C++, SystemC or Python, and enough SystemVerilog to review micro-architecture and RTL.
- PPA trade-off experience on advanced nodes (7nm, 5nm or 3nm) working closely with physical design.
- Clear spec writing and the ability to present architecture to customer engineering leaders and executives.
Preferred qualifications
- Architect on a 51.2T or larger switch generation, or on a design using 224G SerDes.
- AI/ML back-end fabric experience: adaptive routing, packet spraying, collective-aware features, (UEC) specification work.
- Programmable packet pipelines (P4 or a proprietary equivalent).
- Multi-die or chiplet designs (UCIe), and familiarity with co-packaged optics (CPO) or linear pluggable optics (LPO).
- Telemetry and timing: in-band network telemetry, sFlow, high-precision timestamping.
- Security engines such as MACsec or IPsec.
- SONiC, SAI or network operating system integration.
- Contributions to IEEE 802.3, UEC or OCP, or patents in switching and networking.
- Experience in customer-facing or design-services roles.
Tekshapers is an equal opportunity employer and will consider all applications without regards to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.
