Sr. Principal AI Interconnect Architect

Key Responsibilities
Define and engineer high-speed networking and communication systems for AI Inference infrastructure including servers, racks, and chips
Develop architectures for chip-to-chip interconnects and switched fabrics tailored for AI/ML scale-out
Analyze trade-offs in bandwidth, latency, power, area, and reliability
Specify innovative scale-out architectures for optimizing power, cost, and performance
Participate in industry standard bodies and contribute, influence, and shape the direction of industry specifications
Work with SoC, package design, and software teams to ensure seamless integration
Apply familiarity with fabric topologies such as Fat tree, Leaf-Spine (Clos), Torus, and Meshed to various workload and system configurations
Develop performance models for modeling and simulation

Required Qualifications
10+ years of experience
Master's Degree in Electrical Engineering
Master's Degree in Computer Engineering
Master's Degree in Computer Science
Ph.D. in Electrical Engineering
Ph.D. in Computer Engineering
Ph.D. in Computer Science
AI Hardware Architecture

Skills
Interconnect Technology Development
Switching Fabrics
Software Defined Networking
Ethernet and Ultra-Ethernet Networking
Performance Modeling and Simulation
GPU and Accelerator Cluster Architecture
AI Hardware Architecture
Standards Body Participation
Cross-functional Collaboration
Fabric Topology Design