Milpitas, California
•
Today
Key Responsibilities Responsible for driving the HBF ASIC architecture that integrates the AI Storage with GPU/TPU/xPU accelerators Author architecture specifications in clear and concise language for AI/ML xPU based Accelerator using AI Storage Solutions Define SoC subsystem, software, firmware interactions with embedded subsystems, and SoC CPUs LLM Workload analysis and characterization of ASIC to identify opportunities for performance improvement Work with RTL/DV/Simulation/Emulation/FW
Easy Apply
Full-time
DOE
