AI/ML ASIC Architect

Key Responsibilities
Responsible for driving the HBF ASIC architecture that integrates the AI Storage with GPU/TPU/xPU accelerators
Author architecture specifications in clear and concise language for AI/ML xPU based Accelerator using AI Storage Solutions
Define SoC subsystem, software, firmware interactions with embedded subsystems, and SoC CPUs
LLM Workload analysis and characterization of ASIC to identify opportunities for performance improvement
Work with RTL/DV/Simulation/Emulation/FW teams to evaluate architectural changes and assess performance, power, area, and endurance of the product

Required Qualifications
9+ years of experience
Bachelors Degree in Computer/Electrical Engineering

Skills
ASIC Architecture
SoC Architecture
UCIe
2.5D/3D Package System Integration
Computer and Graphics Architecture
LLMs
GPU/TPU Accelerators
High Bandwidth Memory Hierarchy Optimization
KV Cache Optimizations
RTL/DV/Simulation/Emulation Evaluation
Firmware and Embedded Subsystem Integration
Architecture Specification Authoring
LLM Workload Analysis and Characterization
Performance Power Area Endurance Assessment
Cross-functional Collaboration

Schedule
Start date: 2026-11-18