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STA Lead Static Timing Analysis

Metalight Solutions Inc

Remote • Today

Easy Apply

Contract

Depends on Experience

Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead

Altera Corp.

San Jose, California • Today

Full-time

USD 187,000.00 - 270,000.00 per year

Senior/Lead STA Engineer - Austin, TX - Onsite

Lorven Technologies, Inc.

Austin, Texas • 15d ago

Easy Apply

Third Party, Contract

$60 - $80

Metalight Solutions Inc

Job Details

Skills

ASIC
DFT
Debugging
Integrated Circuit
Optimization
Physical Data Model
Python
RTL
Reporting
Scripting
Signal Integrity
Static Timing Analysis
Synopsys
System On A Chip
Tcl
Timing Closure

Summary

STA Lead Static Timing Analysis

Location: Remote
Job Type: Contract

Job Summary

We are looking for an experienced STA Lead to lead Static Timing Analysis, timing signoff, and timing closure activities for complex ASIC/SoC designs. This role will be responsible for driving timing methodology, developing and validating timing constraints, analyzing MMMC scenarios, and ensuring designs meet timing requirements through tape-out.

The ideal candidate should have strong hands-on experience with Synopsys PrimeTime, SDC constraints, timing closure, Signal Integrity (SI), crosstalk, OCV/AOCV/POCV, and Timing ECOs.

Key Responsibilities

Lead STA methodology, timing signoff, and timing closure from block level through full-chip level.
Develop, validate, and maintain SDC timing constraints and signoff flows.
Perform detailed setup and hold analysis across multiple MMMC scenarios.
Drive timing optimization and closure for complex ASIC/SoC designs.
Perform signoff analysis using Synopsys PrimeTime, PrimeTime-SI, and PBA.
Debug and resolve timing issues related to signal integrity, crosstalk, noise, OCV, AOCV, and POCV.
Participate in clock architecture reviews and analyze cross-domain timing paths.
Generate, analyze, and validate Timing ECOs to achieve timing closure.
Support timing signoff reviews and provide timing statrecommendations for tape-out.
Develop and maintain automation for timing analysis, reporting, and debugging using TCL and/or Python.
Work closely with Physical Design, RTL, DFT, and other engineering teams to resolve timing issues.
Support advanced technology-node designs and full-chip timing closure through tape-out.

Required Qualifications

Strong hands-on experience in Static Timing Analysis (STA) and ASIC/SoC timing signoff.
Expert-level experience with Synopsys PrimeTime.
Experience with PrimeTime-SI and PBA.
Strong understanding of SDC constraints and MMMC methodology.
Hands-on experience with setup/hold analysis and timing closure.
Strong knowledge of SI, crosstalk, noise, OCV, AOCV, and POCV.
Experience with clock timing and cross-domain analysis.
Strong experience with Timing ECO implementation and validation.
Proficiency in TCL and/or Python scripting for STA automation and reporting.
Experience supporting complex ASIC/SoC designs through timing signoff and tape-out.

Preferred Qualifications

Experience with advanced technology nodes.
Strong understanding of the physical design flow and timing-driven implementation.
Experience working on full-chip designs and complete tape-out cycles.
Experience collaborating with cross-functional ASIC/SoC design teams.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91172362
Position Id: 9094817
Posted 3 hours ago

Company Info

About Metalight Solutions Inc

Metalight Solutions is a modern talent solutions partner helping organizations across the US and Canada build high-performing teams through intelligent, scalable hiring solutions. We specialize in delivering top-tier talent across IT, Non-IT and Engineering domains, supporting businesses in fast-moving and competitive markets.

By combining high-level sourcing strategies, deep market intelligence, and human expertise, we identify candidates who are not only qualified, but aligned with business goals, culture, and long-term success. From Contract, C2C, Contract-to-Hire, to Permanent Hiring, we provide agile workforce solutions designed for today’s evolving business needs.

Our approach is built on speed, precision, and quality execution. With strong talent networks, data-driven recruitment strategies, and a delivery-focused mindset, we help clients close critical roles faster while maintaining hiring excellence.

We partner with startups, staffing firms, SMBs, and enterprise organizations, adapting seamlessly to diverse hiring models while ensuring transparency, responsiveness, and accountability at every stage.

At Metalight Solutions, we go beyond staffing, we enable growth by connecting businesses with the right talent, powered by technology and driven by results.

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Aman Dhangar

Recruiter @ Metalight Solutions Inc

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Metalight Solutions Inc

Job Details

Skills

ASIC
DFT
Debugging
Integrated Circuit
Optimization
Physical Data Model
Python
RTL
Reporting
Scripting
Signal Integrity
Static Timing Analysis
Synopsys
System On A Chip
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Summary

STA Lead Static Timing Analysis

Location: Remote
Job Type: Contract

Job Summary

The ideal candidate should have strong hands-on experience with Synopsys PrimeTime, SDC constraints, timing closure, Signal Integrity (SI), crosstalk, OCV/AOCV/POCV, and Timing ECOs.

Key Responsibilities

Lead STA methodology, timing signoff, and timing closure from block level through full-chip level.
Develop, validate, and maintain SDC timing constraints and signoff flows.
Perform detailed setup and hold analysis across multiple MMMC scenarios.
Drive timing optimization and closure for complex ASIC/SoC designs.
Perform signoff analysis using Synopsys PrimeTime, PrimeTime-SI, and PBA.
Debug and resolve timing issues related to signal integrity, crosstalk, noise, OCV, AOCV, and POCV.
Participate in clock architecture reviews and analyze cross-domain timing paths.
Generate, analyze, and validate Timing ECOs to achieve timing closure.
Support timing signoff reviews and provide timing statrecommendations for tape-out.
Develop and maintain automation for timing analysis, reporting, and debugging using TCL and/or Python.
Work closely with Physical Design, RTL, DFT, and other engineering teams to resolve timing issues.
Support advanced technology-node designs and full-chip timing closure through tape-out.

Required Qualifications

Strong hands-on experience in Static Timing Analysis (STA) and ASIC/SoC timing signoff.
Expert-level experience with Synopsys PrimeTime.
Experience with PrimeTime-SI and PBA.
Strong understanding of SDC constraints and MMMC methodology.
Hands-on experience with setup/hold analysis and timing closure.
Strong knowledge of SI, crosstalk, noise, OCV, AOCV, and POCV.
Experience with clock timing and cross-domain analysis.
Strong experience with Timing ECO implementation and validation.
Proficiency in TCL and/or Python scripting for STA automation and reporting.
Experience supporting complex ASIC/SoC designs through timing signoff and tape-out.

Preferred Qualifications

Experience with advanced technology nodes.
Strong understanding of the physical design flow and timing-driven implementation.
Experience working on full-chip designs and complete tape-out cycles.
Experience collaborating with cross-functional ASIC/SoC design teams.

Dice Id: 91172362
Position Id: 9094817
Posted 3 hours ago

Company Info

About Metalight Solutions Inc

At Metalight Solutions, we go beyond staffing, we enable growth by connecting businesses with the right talent, powered by technology and driven by results.

Go to company profile

Fitment