Senior/Lead STA Engineer
Austin, TX - Onsite
Contract: 12+ Months
Required Qualifications
• 12–18 years of experience in semiconductor/ASIC design with significant hands-on STA experience.
• Strong understanding of static timing analysis and timing signoff methodologies.
• Expert knowledge of Synopsys PrimeTime or equivalent STA tools.
• Strong expertise in SDC constraints, clock definitions, timing exceptions, and MCMM analysis.
• Deep understanding of setup/hold analysis, clock timing, OCV/AOCV/POCV, CPPR, SI/crosstalk, and variation effects.
• Experience with advanced-node timing closure and complex SoC designs.
• Strong understanding of synthesis, physical design, CTS, routing, and ECO flows.
• Proficiency in Tcl scripting; Python or Perl experience is a plus.
• Strong analytical and problem-solving skills.
• Excellent communication and cross-functional collaboration skills.
Preferred Qualifications
• Experience leading STA/signoff for large, complex SoCs.
• Experience with advanced process technologies and high-performance designs.
• Experience with timing signoff automation and methodology development.
• Strong understanding of low-power design and the interaction between timing and power.
• Prior technical leadership or mentoring experience.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
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