Digital CAD Flow Developer

Job Title: Digital CAD Flow Developer Location: Remote Employment Type: Contract

Job Summary

We are looking for an experienced Digital CAD Flow Developer to develop, enhance, automate, and support RTL-to-GDSII implementation flows for advanced SoC designs.

The ideal candidate will have strong experience with Synopsys Reference Methodology (RM) and hands-on expertise in digital implementation flows. You will work closely with design, CAD, physical design, and EDA teams to improve flow efficiency, troubleshoot complex issues, and develop scalable automation solutions.

Key Responsibilities

• Develop, maintain, customize, and optimize RTL-to-GDSII implementation flows.
• Work with Synopsys Reference Methodology (RM) and digital implementation/signoff flows.
• Develop automation and methodology improvements across different implementation stages.
• Support at least two or more of the following areas:
  • RTL / CDC
  • Logic Synthesis
  • DFT
  • Floorplanning
  • Placement & Routing (P&R)
  • Clock Tree Synthesis (CTS)
  • Power Optimization
  • Physical Verification
  • Static Timing Analysis / Timing Closure
  • Formal / Equivalence Checking
• Debug complex design, flow, and EDA tool issues and perform root-cause analysis.
• Develop scalable scripts, utilities, parsers, and automation for large-scale SoC implementation.
• Work with design data formats such as Verilog and DEF.
• Optimize scripts and flows for performance when working with large designs.
• Create technical documentation and provide training/support to engineering teams.
• Present technical solutions and methodology improvements to engineering and management teams.
• Collaborate with Design, CAD, Physical Design, and EDA vendors to resolve flow and technology-related challenges.

Required Qualifications

• Strong experience developing or supporting digital ASIC/SoC implementation flows.
• Hands-on experience with RTL-to-GDSII flow development and automation.
• Strong scripting/programming skills in several of the following:
  • Tcl
  • Python
  • Perl
  • Shell
  • AWK
  • Make
  • C/C++
• Experience developing parsers and automation utilities for design data such as Verilog, DEF, or similar formats.
• Experience working with large-scale SoC designs.
• Strong debugging and root-cause analysis skills.
• Ability to troubleshoot complex EDA tool and flow issues.
• Strong communication, documentation, and stakeholder-management skills.

Preferred Qualifications

• Hands-on experience in two or more digital implementation domains such as Synthesis, DFT, Floorplanning, P&R, CTS, Timing Closure, Physical Verification, or Equivalence Checking.
• Experience with Synopsys digital implementation and signoff tools.
• Experience working with Synopsys Reference Methodology (RM).
• Experience presenting technical papers, methodologies, or technical solutions at conferences or engineering forums.