Role : Senior DFT Engineer Location : Remote Candidates should preferably be based in the PST time zone (California preferred). Duration : Long term The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains.