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358 results (15 new)

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ASIC/RTL Design Engineer

Saicon Consultants Inc.

San Jose, California • Yesterday

Easy Apply

Contract, Third Party

Depends on Experience

Senior ASIC RTL DESIGN Engineer

Carlton National Resources, INC

Remote or Hybrid in Boston, Massachusetts • Yesterday

Easy Apply

Contract

90 - 130

Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

Tanisha Systems, Inc.

San Jose, California • 9d ago

Easy Apply

Contract, Third Party

Depends on Experience

RTL Design Engineer

Technical Link

Remote • 3d ago

Easy Apply

Contract

Depends on Experience

Sr. Engineer, ASIC Design

Ayar Labs

San Jose, California • Today

Full-time

USD 160,000.00 - 192,000.00 per year

Sr. Staff Engineer, ASIC Design

Ayar Labs

San Jose, California • Today

Full-time

USD 180,000.00 - 223,000.00 per year

Principal Engineer, ASIC Design

Micron Technology, Inc.

San Jose, California • Today

Full-time

USD 198,000.00 - 336,000.00 per year

ASIC Implementation Engineer PD

Broadcom Corporation

San Jose, California • Today

Full-time

USD 121,900.00 - 195,000.00 per year

Physical Design Engineer

Search Tactics LLC

San Jose, California • 15d ago

Easy Apply

Third Party

$$70-$80 C2C

ASIC Implementation Engineer STA

Broadcom Corporation

San Jose, California • Today

Full-time

USD 143,800.00 - 230,000.00 per year

Physical Design Engineer – Contract (USC)

TechCafeHub LLC

Hybrid in San Jose, California • Yesterday

Easy Apply

Contract

75 - 85

ASIC Verification Engineer (Remote - USA)

Encore Semi Inc

Remote or Santa Clara, California • 5d ago

Full-time

USD 120,000.00 - 135,000.00 per year

Senior Physical Design Engineer

Vastika Inc.

Sunnyvale, California • 7d ago

Easy Apply

Full-time

140000 - 170000

Senior CPU RTL Engineer

Qualcomm Technologies

Santa Clara, California • Today

Full-time

USD 142,200.00 - 213,400.00 per year

ASIC Verification Engineer

Axiado

San Jose, California • Today

Full-time

Physical Design Engineer & DV Engineers

K-Tek Resourcing LLC

Sunnyvale, California • 11d ago

Easy Apply

Full-time

160,000 - 170,000

ASIC Emulation Engineer

R Cube Creative Consulting Inc

San Jose, California • 9d ago

Easy Apply

Contract

60 - 75

Principal Digital RTL Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 185,000.00 - 240,000.00 per year

ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX

Palo Alto, California • Today

Full-time

USD 135,000.00 - 175,000.00 per year

CPU RTL LLC Engineer

Qualcomm Technologies

Santa Clara, California • Today

Full-time

USD 198,700.00 - 298,100.00 per year

Senior Engineer, Digital Design Engineering

Analog Devices, Inc.

San Jose, California • Today

Full-time

USD 156,853.00 - 201,756.00 per year

Senior FPGA Design Engineer

Axiado

San Jose, California • Today

Full-time

Senior Front End Design Engineer (Microarchitecture) - Sunnyvale HQ

Cerebras Systems

Sunnyvale, California • Today

Full-time

USD 250,000.00 - 300,000.00 per year

Design Verification Engineer

HCP ONE LLC

San Jose, California • 9d ago

Easy Apply

Contract

Depends on Experience

Principal Engineer, Design Verification - DDR Memory Subsystems

Altera Corp.

San Jose, California • Today

Full-time

USD 209,500.00 - 299,200.00 per year

Design Verification Engineer III

BCforward

Sunnyvale, California • Yesterday

Easy Apply

Contract

$65.32 - $65.32 per hour

Senior Engineer, GPU RTL Design - Pixel Pipe

Samsung Electronics America

San Jose, California • Today

Full-time

USD 139,000.00 - 208,400.00 per year

Design Engineer

Aditi Consulting

Sunnyvale, California • Today

Easy Apply

Contract, Third Party

$82 - $85

Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI)@San Jose

Ekcel Systems

San Jose, California • Today

Easy Apply

Third Party, Contract

60+

Senior Principal Engineer, Micro-architecture and RTL

Marvell Semiconductor Inc.

Santa Clara, California • Today

Full-time

USD 182,360.00 - 273,200.00 per year

Job Details

Skills

Summary

Job Description:

The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and *** internal IPs.
Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.

EXPERIENCE AND EDUCATION:

SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.
Working knowledge of ARM cores and other I/O standard interfaces. An ideal candidate would also exhibit
Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership. 10+ years of experience.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: saicon
Position Id: 26-88324
Posted 1 day ago

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ASIC/ SoC RTL Design Engineer

Hybrid in Burlingame, California

•

7d ago

Title: ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams. Must haves: 8 12+ years in ASIC/SoC digital design with hands-on RTL ownershipStrong Sy

Easy Apply

Contract

$83 - $93

Physical Design Engineer

San Jose, California

•

15d ago

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering

Easy Apply

Third Party

$$70-$80 C2C

Physical Design Engineer – Contract (USC)

Hybrid in San Jose, California

•

Yesterday

Physical Design Engineer ContractIntroduction: We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering teams. Responsibilities: Execute RTL synthesis for complex ASIC and SoC d

Easy Apply

Contract

75 - 85

Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI)@San Jose

San Jose, California

•

Today

Hi, Hope you are doing well. We have the position below. Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI) Location: San JoseDuration would be 6 months to start and can be extended to 18 months. OnsiteDepartment: Hardware / SoC Design |Level: Senior (8+ years) Role Summary We are looking for a Principal Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with deep expertise in the ARM CHI-G (Coherent Hub Interface Gateway) protoco

Easy Apply

Third Party, Contract

60+

More jobs at Saicon Consultants Inc. in San Jose, CA

Job Details

Skills

Summary

Job Description:

The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and *** internal IPs.
Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.

EXPERIENCE AND EDUCATION:

SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.
Working knowledge of ARM cores and other I/O standard interfaces. An ideal candidate would also exhibit
Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership. 10+ years of experience.

Dice Id: saicon
Position Id: 26-88324
Posted 1 day ago

Fitment

Dice Job Match Score™

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Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

ASIC/ SoC RTL Design Engineer

Hybrid in Burlingame, California

•

7d ago

Easy Apply

Contract

$83 - $93

Physical Design Engineer

San Jose, California

•

15d ago

Easy Apply

Third Party

$$70-$80 C2C

Physical Design Engineer – Contract (USC)

Hybrid in San Jose, California

•

Yesterday

Easy Apply

Contract

75 - 85

Principal/Lead Design Engineer Memory Controller-(CHI-G / DFI)@San Jose

San Jose, California

•

Today

Easy Apply

Third Party, Contract

60+

More jobs at Saicon Consultants Inc. in San Jose, CA