ASIC/RTL Design Engineer

Title: ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams. Must haves: 8 12+ years in ASIC/SoC digital design with hands-on RTL ownershipStrong Sy

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering

THE MUST SKILL THEY SHOULD BE STRONG WITH IS Cadence Genus. Physical Design Engineer (Contract) Position Overview We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering teams.

Physical Design Engineer ContractIntroduction: We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering teams. Responsibilities: Execute RTL synthesis for complex ASIC and SoC d