Search Jobs | Dice.com

263 results (41 new)

Group by company

ASIC Design/SDC Engineer

Inabia Software & Consulting Inc.

San Jose, California • Today

Easy Apply

Third Party, Contract

Depends on Experience

Principal ASIC Verification Engineer

Dexian DISYS

San Jose, California • Today

Easy Apply

Contract

$95 - $100 per hour

ASIC/RTL Design Engineer 5

Black Rock Group

San Jose, California • 8d ago

Easy Apply

Third Party, Contract

Depends on Experience

ASIC/RTL Design Engineer Analog & Mixed-Signal Modeling (SystemVerilog/UVM)

VGAI Solutions Inc

San Jose, California • Today

Easy Apply

Contract

70 - 75

ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs

Annapurna Labs (U.S.) Inc.

Cupertino, California • Today

Full-time

Physical Design Engineer Semiconductor / ASIC

Metalight Solutions Inc

Hybrid in Palo Alto, California • 13d ago

Easy Apply

Contract

$70 - $90

ASIC Design Verification Engineer - W2 Contract

XFORIA Inc

Menlo Park, California • 7d ago

Easy Apply

Contract

Depends on Experience

Lead ASIC Verification Engineer

System One

Hybrid in San Jose, California • Today

Easy Apply

Contract

75 - 85

Design Verification Engineer

Inabia Software & Consulting Inc.

San Jose, California • Today

Easy Apply

Third Party, Contract

Depends on Experience

ASIC Verification Engineer

Cornelis Networks

San Jose, California • Today

Full-time

Senior Staff ASIC Verification Engineer-18604

Synopsys, Inc.

Sunnyvale, California • Today

Full-time

Principal ASIC Verification Engineer

Cornelis Networks

San Jose, California • Today

Full-time

ASIC Emulation Engineer

AMD (Advanced Micro Devices)

Santa Clara, California • Today

Full-time

USD 145,600.00 per year

Verification Engineer ASIC/CPU/GPU Functional Verification

VGAI Solutions Inc

San Jose, California • Today

Easy Apply

Contract

75 - 80

Physical Design Engineer

FSTONE Technologies

Hybrid in Sunnyvale, California • Yesterday

Easy Apply

Contract, Third Party

Depends on Experience

Senior Chip Lead Engineer-SoC/ASIC

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 143,500.00 per year

ASIC DFT Engineer

Rivian

Palo Alto, California • Today

Full-time

Compensation information provided in the description

Physical Design Engineer (Top-Level / Full-Chip) - AS

Central Business Solutions

San Jose, California • 2d ago

Easy Apply

Full-time

Depends on Experience

Hardware Design & Failure Analysis Engineer

SysMind, LLC

San Jose, California • 8d ago

Easy Apply

Contract, Third Party

$66 - $70

Sr. Staff Engineer, ASIC Design

Ayar Labs

San Jose, California • Today

Full-time

USD 180,000.00 - 223,000.00 per year

Physical Design Engineer

Cystems Logic

Sunnyvale, California • 6d ago

Easy Apply

Contract, Third Party

Senior Physical Design Engineer

RyanBPM

Sunnyvale, California • Today

Easy Apply

Full-time

Depends on Experience

Hardware Design and Failure Analysis Engineer

Galaxy i Technologies, Inc.

San Jose, California • 13d ago

Contract, Third Party

Depends on Experience

Physical Design Engineer

cloudingest inc

Sunnyvale, California • 12d ago

Easy Apply

Third Party, Contract

Depends on Experience

Physical Design Engineer

Cystems Logic

Sunnyvale, California • 6d ago

Easy Apply

Contract, Third Party

ASIC RTL DESIGN Engineer

Carlton National Resources, INC

Remote • 7d ago

Easy Apply

Contract

100 - 140

Principal Engineer, SOC Design

Samsung Electronics America

San Jose, California • Today

Full-time

USD 219,000.00 - 351,000.00 per year

ASIC Design Lead / Senior Chip Design Engineer

Virisha LLC

Remote • 14d ago

Easy Apply

Contract

95 - 105

Senior Physical Design Engineer

GLOBAL IT CON LLC

Sunnyvale, California • Today

Easy Apply

Full-time

180,000 - 200000

Physcial Design Engineer

Arrow Electronics, Inc.

San Jose, California • Today

Full-time

Job Details

Skills

ASIC
DFT
Digital Design
Change Data Capture
IP
Formal Verification
FC
Integrated Circuit
Intellectual Property
RTL
Physical Data Model
Scripting
SystemVerilog
Python
Perl
Synopsys
Static Timing Analysis
Cadence
SpyGlass
ASIC Design Engineer
SDC Engnieer

Summary

You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you’ll contribute to developing next-generation networking chips.

Responsibilities include:

Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Creating fullchip clocking diagrams and related documentation.

Minimum Qualifications

Bachelor’s Degree in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master’s Degree in Electrical or Computer Engineering with 5+ years of ASIC or related experience
Experience with block/full chip SDC development in functional and test modes.
Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
Understanding of related digital design concepts (eg. clocking and async boundaries)
Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming

Preferred Qualifications

Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
Experience with Spyglass CDC and glitch analysis
Experience using Formal Verification: Synopsys Formality and Cadence LEC.
Experience with scripting languages such as Python, Perl, or TCL

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10337997
Position Id: 9133712
Posted 22 hours ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

Contact the job poster

Adhunika Sharma

Recruiter @ Inabia Software & Consulting Inc.

View Profile

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Hybrid in Palo Alto, California

•

13d ago

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

Easy Apply

Contract

$70 - $90

Senior RTL / STA Engineer

San Jose, California

•

Today

Position: Senior RTL / STA Engineer Location: San Jose, California (on-site preferred) Duration:12+ months No.of Positions: 1 Role Overview Ciscos ASIC Engineering group is seeking a senior RTL / Static Timing Analysis (STA) contractor to support timing constraint development and verification, RTL design, and timing closure across ASIC design flows. Key Responsibilities Develop, review, debug, and verify timing constraints for ASIC designs. Contribute to RTL design and collaborate with design,

Easy Apply

Contract

Depends on Experience

RTL/STA Engineer

San Jose, California

•

2d ago

Position: Senior RTL / STA Engineer Location: San Jose, California (on-site preferred), USA Role Overview Ciscos ASIC Engineering group is seeking a senior RTL / Static Timing Analysis (STA) contractor to support timing constraint development and verification, RTL design, and timing closure across ASIC design flows. The preferred work location is Ciscos San Jose campus. Candidates with at least 8 years of relevant experience are preferred; candidates with somewhat less experience may be consider

Easy Apply

Full-time, Third Party

0 - 0

Physical Design Engineer

Santa Clara, California

•

8d ago

Hiring: Physical Design Engineer We are looking for an experienced Physical Design Engineer to work on advanced technology nodes and high-performance IP designs. Key Responsibilities - Execute RTL-to-GDSII implementation, including synthesis, place and route, timing optimization, and physical verification. - Perform floorplanning, Clock Tree Synthesis (CTS), clock gating, and buffer/repeater insertion. - Optimize designs for Power, Performance, and Area (PPA). - Support scan stitching, logic equ

Easy Apply

Third Party, Contract

Depends on Experience