We are looking for a highly experienced ASIC Verification Engineer to support functional verification activities for complex ASICs and IP cores as part of a next-generation CPU/GPU development program.
The ideal candidate will have strong experience in hardware verification, C/C++ development, Linux environments, and debugging complex systems. You will collaborate closely with design and verification teams to understand design specifications, develop test plans, execute functional tests, and ensure the quality and reliability of advanced SoC designs.
Key Responsibilities
Participate in functional verification of complex ASIC blocks and IP cores for CPU/GPU development.
Work closely with design and verification engineers to understand and validate functionality at block, chip, and system levels.
Develop, document, and execute comprehensive verification test plans.
Create and run directed and constrained-random tests through simulation.
Identify, debug, and resolve functional issues using appropriate debugging tools.
Apply hardware modeling and assertion-based verification methodologies.
Work within existing verification environments and infrastructure.
Adopt evolving industry verification methodologies to support increasingly complex SoC designs.
Collaborate with cross-functional teams to meet project milestones and aggressive development schedules.
Required Skills & Qualifications
10+ years of experience in ASIC functional verification or software/firmware development within a hardware development environment.
Strong programming experience in C/C++ within a Linux environment.
Excellent debugging skills with tools such as GDB and Valgrind.
Proficiency in Object-Oriented Programming (OOP), STL, and data structures.
Strong understanding of computer architecture and hardware fundamentals.
Experience with Perl scripting and Makefiles.
Strong analytical, problem-solving, and troubleshooting skills.
Excellent written and verbal communication skills.
Preferred / Nice-to-Have Skills
Experience with Verilog, SystemVerilog, or SystemC.
Knowledge of C/Verilog integration using DPI/PLI.
Experience with assertion-based verification and hardware modeling.
Background in complex ASIC, CPU, GPU, or SoC development projects.
Ideal Candidate Profile
A senior-level engineer with a strong combination of C/C++ programming, Linux-based development, hardware/ASIC verification, and low-level debugging experience, preferably within CPU/GPU or complex SoC development environments.
Location Requirement: San Jose, CA – Onsite position.
