Verification Engineer 4

Verification Engineer 4 - 1 - San Jose

Experience - 8-10 Years preferable

JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.

Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.

Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.

Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules,

and work within the existing verification infrastructure on currently active projects. Be familiar with hardware modeling and/or assertion-based verification methods.

EXPERIENCE AND EDUCATION:

• 8-10 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting;
• Strong background in C/C++ development in a Linux Environment;Strong debug skills and experience with debug tools such as Gdb, Valgrind;
• Proficient in Object Oriented programming, STL, computer architecture and data structures;Knowledge of Perl and Makefiles;
• Experience in Verilog/SystemVerilog/SystemC, preferred;Experience in C/Verilog environment using DPI/PLI, preferred;
• Strong analytical skills and attention to detail; Excellent written and communication skills
• Comments for Suppliers: Prefer SoC verification experience and UVM. (System Verilog)

Fully onsite in San Jose CA.

Manager is open to candidates with around 5 years of experience.

Pluses: Ethernet, PCIe, PHY, and DFX