ASIC/RTL Design Engineer Analog & Mixed-Signal Modeling (SystemVerilog/UVM)

We are seeking an experienced ASIC/RTL Design Engineer with strong hands-on expertise in RTL coding, Analog/Mixed-Signal Design, and SystemVerilog Behavioral Modeling.

The ideal candidate will have experience developing behavioral models of complex analog and mixed-signal circuits, including PLLs, ADC/DAC, clocking circuits, and high-speed SerDes TX/RX analog front ends.

You will work closely with Analog Design, RTL Design, and Verification teams to develop, integrate, and validate high-performance models within a SystemVerilog UVM verification environment.

Key Responsibilities

• Develop behavioral SystemVerilog models for analog and mixed-signal circuits, including PLLs, ADC/DAC, clocking, TX/RX front ends, and calibration loops.

• Read and interpret circuit schematics, netlists, and specifications to develop accurate behavioral models.

• Design model architectures balancing simulation accuracy, performance, and speed.

• Integrate and validate behavioral models within SystemVerilog/UVM verification environments.

• Compare behavioral model results against transistor-level simulation results.

• Debug simulation failures using waveforms and identify root causes across models, RTL, and testbenches.

• Collaborate with Analog, RTL, and Verification engineers on advanced CMOS and high-speed SerDes/SoC IP designs.

• Document model functionality, interfaces, assumptions, and limitations.

Required Skills & Experience

• 10+ years of relevant ASIC/RTL Design and Verification experience.

• Strong hands-on experience in RTL coding and SystemVerilog.

• Proven experience developing behavioral models of analog and mixed-signal circuits.

• Strong understanding of analog/mixed-signal circuit fundamentals.

• Working knowledge of SystemVerilog UVM methodology.

• Experience debugging simulation failures and analyzing waveforms.

• Hands-on experience with simulation tools such as:

  • Synopsys VCS

  • LTspice

  • HSPICE

Preferred Qualifications

• Experience with high-speed SerDes and SoC IP.

• Knowledge of PLLs, ADC/DAC, clocking circuits, and TX/RX analog front-end design.

• Experience working with advanced CMOS technologies.

• Ability to collaborate with Analog Circuit Design, RTL, and Verification teams.