ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we're looking for talent who feel the same: people who want to leave the planet better than they found it, those who don't shy away from humanity's challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you're designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger - technology that moves the world forward.
THE ROLE: As a Senior ASIC Verification Engineer, you will help bring to life cutting-edge FPGA, ASICs for variety of target customers. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, PD teams, and product engineers to achieve first pass silicon success.
THE PERSON:You have a passion for modern, complex IP architectures, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBLITIES:- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified for PCIe CXL based IP's
- Develop test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Code IP or SS level UVM based testbenches, verification components - monitors, scoreboard, checkers
- Build the directed and random verification tests
- Run regressions, debug test failures towards ensuring high design functional, performance and implementation quality
PREFERRED EXPERIENCE:- Experience with PCIe or CXL or NVMe or ethernet protocols is a must
- Proficient in IP level ASIC verification
- Expert in Verilog, System Verilog, Object Oriented programming
- Expertise in developing UVM based verification frameworks and testbenches
- Scripting and automation of verification processes and flows
- Exposure to leadership or mentorship is an asset
- Experience working in a team environment through the ASIC / FPGA Project lifecycle from Planning to Tape Out
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Good Computer Architecture, systems knowledge
- Comfortable in python / perl and editing / maintaining scripts
- Strong communication skills and the ability to work independently as well as in a cross-site team environment
- Exposure to generative AI or simulation tools for test, testbench, assertion, test plan generation or performance optimization is a plus
ACADEMIC CREDENTIALS:- Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION: - San Jose, CA,
- Candidates located in San Diego, CA; Austin, TX; or Longmont, CO may be considered for more senior-level experienced candidates.
#LI-EV1#LI-HYBRID Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.
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