RTL Verification Engineer

We are seeking a Senior RTL Verification Engineer with strong SoC-level verification experience. The ideal candidate will have hands-on expertise in verifying complex SoC designs, with a strong background in one or more of the following areas: Reliability, Availability & Serviceability (RAS), cache/memory coherency, or hardware security. The candidate should be experienced in developing and executing verification strategies for complex RTL/IP blocks and SoC-level environments. Senior RTL Verific

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Position: Design Verification Engineer Location: San Jose, CA/Austin TX (Onsite) Duration: Contract 10+ Years' Experience Required Job Description Strong in SoC verification Exp in CPU Sub systems verification. Should have worked on ARM processor Should have expertise in SV and UVM Should be well versed in AMBA bus protocols Good debugging skills Experience in High Speed IOs (PCIe, UCIe, DDR, MIPI etc.) is a plus

At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale. Cornelis Networks delivers the world's highest performance scale-out networking solutions for AI and HPC datacenters. Our d