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Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

Tanisha Systems, Inc.

San Jose, California • Today

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Third Party, Contract

Depends on Experience

Job Details

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Summary

Hello Professional,

Good Afternoon!!!

Please find the job description give below, if interested please share me your most updated copy of resume.

Role: Lead ASIC DFT Engineer
Work Setup: Remote, PST time zone preferred
Experience Required:

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

Key Pointers

DFT Architecture definition.
Scan & compression(EDT) implementation
LBIST implementation and verification
Coverage improvements (Spyglass work)
ATPG sims - timing & no timing.
Full chip / Sub system level DFT activities.

Key Skills Required:

Strong hands-on ASIC DFT experience with end-to-end ownership
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
MBIST implementation and verification; SMS experience preferred
Tessent/SSN experience preferred
Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
Post-silicon debug and silicon bring-up experience

TCL, PERL, or Python scripting experience is highly preferred

Shivam Maheshwari
Talent Acquisition Manager, Tanisha Systems Inc
ISO Certified Company{ ISO 9001:2015}
Office:
Email:
Address:99 Wood Ave South, Suite # 308, Iselin, NJ 08830

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10117909
Position Id: 26-17500
Posted 5 hours ago

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Summary

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

DFT Architecture definition.
Scan & compression(EDT) implementation
LBIST implementation and verification
Coverage improvements (Spyglass work)
ATPG sims - timing & no timing.
Full chip / Sub system level DFT activities.

Key Skills Required:

Strong hands-on ASIC DFT experience with end-to-end ownership
Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug
Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools
Strong background in scan insertion, scan chain stitching, ATPG setup, simulation, debug, and DRC analysis
MBIST implementation and verification; SMS experience preferred
Tessent/SSN experience preferred
Strong understanding of PLLs, RTL design, synthesis, LEC, and physical design flows
Post-silicon debug and silicon bring-up experience

TCL, PERL, or Python scripting experience is highly preferred

Shivam Maheshwari
Talent Acquisition Manager, Tanisha Systems Inc
ISO Certified Company{ ISO 9001:2015}
Office:
Email:
Address:99 Wood Ave South, Suite # 308, Iselin, NJ 08830

Dice Id: 10117909
Position Id: 26-17500
Posted 5 hours ago

Fitment

Dice Job Match Score™

⭐ Evaluating experience...

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