12 results (6 new)

Group by company

Comprehensive Resources Inc.

San Jose, California • Today

Easy Apply

Full-time, Part-time, Third Party, Contract

Verification Lead – Memory Controller (CHI-G / DFI)

Goldenpick Technologies LLC

San Jose, California • Today

Easy Apply

Third Party, Contract

$90 - $95

Principal / Lead Design Engineer – Memory Controller (CHI-G / DFI)

Clover Solutions LLC

San Jose, California • Today

Easy Apply

Contract

Depends on Experience

Principal/Lead Design Engineer – Memory Controller (CHI-G / DFI)

Goldenpick Technologies LLC

San Jose, California • Today

Easy Apply

Contract, Third Party

Depends on Experience

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

Ekcel Systems

San Jose, California • 7d ago

Easy Apply

Contract

60+

Verification Lead / Principal Verification Engineer – PCIe Gen5/Gen6

Goldenpick Technologies LLC

San Jose, California • Today

Easy Apply

Contract, Third Party

$90 - $95

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

Comprehensive Resources Inc.

San Jose, California • Today

Easy Apply

Full-time, Part-time, Third Party, Contract

DDR Memory Interface System Validation Lead Engineer

Altera Corp.

San Jose, California • Today

Full-time

USD 149,100.00 - 215,000.00 per year

Senior Verification Engineer

Microsoft Corporation

Mountain View, California • Today

Full-time

USD 119,800.00 - 234,700.00 per year

Sr. FPGA Verification Engineer

Reliable Robotics

Remote or Mountain View, California • Today

Full-time

USD 215,000.00 - 300,000.00 per year

Staff/Principal Engineer - Design Verification (SoC expert/lead)

Micron Technology, Inc.

San Jose, California • Today

Full-time

USD 168,000.00 - 336,000.00 per year

Senior Staff Verification Engineer - PCIe & Memory Subsystems

Marvell Semiconductor Inc.

Santa Clara, California • Today

Full-time

USD 134,390.00 - 201,300.00 per year

Comprehensive Resources Inc.

Job Details

Skills

Memory Controllers
ARM CHI-G
DFI interface
DDR4/DDR5/LPDDR
APB
AHB
AXI4

Summary

Verification Lead - Memory Controller (CHI-G / DFI)

Location: San Jose, CA

Department: Hardware / Design Verification

Level: Lead

Experience: 10+ Years

Job Overview

We are seeking an experienced Verification Lead to own the verification strategy, planning, and execution for a Memory Controller subsystem, with strong expertise in ARM CHI-G and DFI interface verification.

The ideal candidate will lead a team of verification engineers, drive coverage closure and regression, and ensure sign-off quality for memory controller design changes.

Key Responsibilities

Define and own the overall verification strategy and test plan for the memory controller.
Lead development of SystemVerilog/UVM testbenches, scoreboards, checkers, and verification environments.
Verify ARM CHI-G coherency, including request/response/snoop behavior, ordering, and coherency scenarios.
Verify DFI-compliant PHY interfaces, including command/data timing and calibration sequences.
Drive functional, code, and assertion coverage closure.
Coordinate with RTL design teams to understand design changes and update verification plans and regression suites.
Develop and execute formal verification strategies for protocol-critical paths where applicable.
Manage regressions, triage failures, and drive bug closure with Design and DFT teams.
Lead, mentor, and review the work of verification engineers.
Report verification status, risks, and schedule to program management and cross-functional teams.
Own verification documentation, including test plans, coverage models, and sign-off reports.
Support verification activities through tapeout and sign-off.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
10+ years of Design Verification experience.
3+ years in a Verification Lead or management capacity.
Strong hands-on experience verifying DDR4/DDR5/LPDDR memory controllers.
Deep knowledge of ARM CHI/CHI-G protocol verification, including coherency, snoop filtering, and ordering.
Experience verifying DFI-compliant PHY interfaces.
Expert-level SystemVerilog and UVM skills.
Experience building or significantly extending UVM verification environments.
Experience with APB, AHB, AXI4, and/or ACE interfaces.
Strong experience with coverage-driven verification and sign-off processes.
Proven experience leading verification teams through tapeout.

Preferred Qualifications

Experience with formal verification tools for protocol and coherency checking.
Experience correlating pre-silicon verification with post-silicon validation.
Exposure to AI/LLM-assisted verification tools for test generation, coverage analysis, or debug.

How to Apply

Interested candidates can send their updated resume to:

Subject: Verification Lead - Memory Controller

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10123046
Position Id: OOJ - 1782-786-1787327250
Posted 11 hours ago

Company Info

About Comprehensive Resources Inc.

Comprehensive Resources Inc (CRI) is one of the pioneering technology consulting and manpower recruiting firm in New Jersey. We specialize in providing our clients a customized solutions of optimum hiring needs. We are equipped with the most current methods of contract and permanent resources hiring oriented with fixed-priced systems to commercial firms and government agencies.

Go to company profile

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

San Jose, California

•

Today

Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6 Location: San Jose, CA Experience: 10+ Years Job Type: Contract / Long-Term Job Summary We are seeking a Verification Lead / Principal Verification Engineer with strong hands-on experience in PCIe Gen5/Gen6 verification to lead end-to-end verification of PCIe Controller and Subsystem IP. The ideal candidate will have deep expertise in PCIe protocol, UVM, SystemVerilog, LTSSM, PIPE, PHY/SerDes, assertions, coverage closure,

Easy Apply

Full-time, Part-time, Third Party, Contract