Principal / Lead Design Engineer – Memory Controller (CHI-G / DFI)
We’re looking for an experienced Principal / Lead Design Engineer to lead RTL development and architecture updates for our Memory Controller subsystem, with strong expertise in ARM CHI-G (Coherent Hub Interface – Gateway) and DDR/LPDDR/HBM PHY-facing DFI.
🔹 Key Responsibilities:
• Modify and extend existing Memory Controller RTL for new CHI-G and DFI requirements
• Drive microarchitecture updates for command scheduling, arbitration, QoS, and bank/rank management
• Design and integrate CHI-G request, response, and snoop channel logic
• Develop and maintain DFI-compliant PHY-facing interface logic
• Analyze and optimize timing, power, and area
• Drive RTL changes through synthesis and STA closure
• Collaborate with Verification, DFT, and Physical Design teams
• Debug pre-silicon and post-silicon memory controller issues
• Create and maintain microarchitecture specifications and timing diagrams
• Participate in design reviews and mentor junior engineers
🎯 Required Qualifications:
• 8+ years of RTL design experience using SystemVerilog/Verilog
• Hands-on experience with DDR4/DDR5/LPDDR memory controllers or equivalent
• Working knowledge of ARM CHI/CHI-G protocol
• Experience with APB/AHB/AXI4/ACE interfaces
• Experience with DFI specification and PHY-facing interfaces
• Experience modifying/extending large existing RTL codebases
• Familiarity with synthesis, timing closure, and low-power design
• Strong debugging skills using simulation waveforms, formal tools, and lab equipment
⭐ Preferred:
• DFT and post-silicon bring-up experience
• PCB-level memory subsystem validation
• UVM-based verification experience
• AI/LLM-assisted RTL development or design productivity tooling
📍 Location: San Jose, CA
🏢 Department: Hardware / SoC Design
🎓 Education: Bachelor’s/Master’s in Electrical Engineering, Computer Engineering, or related field
shali
+1 Ext. 106
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