We’re Hiring – DFT Engineer
We’re looking for an experienced DFT Engineer with strong hands-on expertise in Siemens Tessent, ATPG, MBIST, Scan, JTAG/IJTAG, and RTL. The ideal candidate will have a strong understanding of DFT methodologies and experience debugging and improving fault coverage.
*Design for Test (DFT) Engineer plays a crucial role in ensuring that integrated circuits (ICs) and systems-on-chip (SoCs) can be thoroughly tested for defects, reliability, and performance.
*Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite.
*Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing.
*Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improvement.
*Experience with MBIST (Memory Built-In Self-Test), including memory test architecture, implementation, and diagnostics.
*Good knowledge of IO Test methodologies for interface and pin-level validation.
*Strong understanding of Clock DFT and clock verification concepts.
*Solid foundation in Digital Design and RTL (Verilog/System Verilog).
*Experience with industry-standard DFT/ATPG EDA tools.
*Experience in verification of DFT features, including Boundary Scan (JTAG), IJTAG, MBIST, High-Speed Scan Testing, and other DFT methodologies.
*Excellent analytical, debugging, and problem-solving skills.
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