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Santa Clara, California

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Today

Role Purpose We are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary Scan Key Responsibilities: Work on Scan insertion, ATPG, GLS (timing/non-timing) Implement MBIST and/or Boundary Scan (BSCAN, JTAG) Support DFT architecture and chip-level integration Debug DFT issues and improve test coverage Requirements: Experience in at least 2 DFT areas (Scan/ATPG/MBIST/BSCAN/GLS) Strong understanding of DFT concepts and flow Exposure to end-to-end DFT is a plus

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Full-time

100,000 - 130,000

Sr DFT Engineer

Santa Clara, California

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6d ago

Hi, Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification] Location : Santa Clara, CA Experience : 4+ Years in DFT Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support client s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engin

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Contract, Third Party

Depends on Experience

Senior Design for Test (DFT) Engineer

Santa Clara, California

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8d ago

Job Title : Senior DFT Engineer Location : Santa Clara, CA Experience : 4+ Years in DFT Skill: [ATPG , MBIST, IO Test, Clock Verification] Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The enginee

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Contract, Third Party

$60 - $70

Senior DFT Engineer

Saratoga, California

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Today

Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We're intentional, we're una

Full-time

USD 120,000.00 - 220,000.00 per year

ASIC DFT Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's ASIC Product Division (APD) is seeking candidates for a DFT position at our San Jose, California, Development Center. The successful candidate will be responsible for leading DFT programs all the way from chip level DFT specification, throug

Full-time

USD 141,300.00 - 226,000.00 per year

Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification]

Santa Clara, California

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16d ago

JobTitle:SeniorDFTEngineer[ATPG,MBIST,IOTest,ClockVerification] Location:SantaClara,CA Experience:4+YearsinDFT JobSummary WeareseekinganexperiencedSeniorDFT/ATPGEngineertosupportNVIDIAshighperformanceGPUandSoCdesigns.TherolefocusesondeliveringrobustDesignforTestability(DFT)solutions,comprehensiveATPG,andadvancedtestfeaturessuchasMBIST,IOTest,andClockVerification,ensuringhighcoverage,yield,andsiliconreliability.TheengineerwillworkcloselywithNVIDIAscrossfunctionalteamstoenablefirsttimerightsilico

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Contract

Depends on Experience

Senior DFT Engineer

Santa Clara, California

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16d ago

Key Responsibilities Architect, implement, and validateDFT solutionsto improve controllability and observability in complex GPU/SoC designsLeadscan-based DFT implementation, including scan insertion, compression, and test logic integrationDevelop and debugATPG patternstargeting stuckat, transition, and additional fault modelsImplement and supportMBIST architecturesfor onchip memory test, diagnosis, and coverage improvementPerformIO Test planning and validationto ensure reliable interface and pin

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Third Party, Contract

Depends on Experience

CPU DFT Verification Engineer

Santa Clara, California

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Today

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our pr

Full-time

DFT Engineer

Remote

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Yesterday

Contract role. 12 months Remote 3 Main priorities below: 1- Tile Based Approach 2-TessentSSN- specificallySSN 3- MCM Packages/Die-To-Die ChipsDFT engineer- Expert with Tessent tools. Experience with TessentSSN. Experience working on ATPG, MBIST, JTAG,DFTInsertion. Experience with ownDFTVerification. Experience with ICL PDL.

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Third Party, Contract

60 - 90

Senior DFT Engineer

Remote

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Today

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep

Full-time

USD 170,000.00 - 250,000.00 per year

CPU DFT Engineer

Santa Clara, California

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Today

Company:Qualcomm Technologies, Inc. Job Area:Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you?ll insure it becomes reality. We?re doing a ground up implementation of a new chip architecture, so you?ll have to ability

Full-time

Compensation information provided in the description

Software Engineer - Systems (DFT Initiative)

Cupertino, California

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Today

Are you interested in working on tools and software that directly enable hardware validation? Our Hardware Test Engineering team is evolving our Design for Test (DFT) methodology, and we're building the software infrastructure to support it effectively.\\n This is an opportunity to develop software tools that control and automate hardware testing. You'll work on designing & building maintainable software that directly interfaces with test hardware and equipment. This isn't high-level applicatio

Full-time

Staff DFT Engineer

Santa Clara, California

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Today

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Full-time

USD 128,000.00 - 189,370.00 per year

Hiring: DFT Lead | 7nm & Below | Saratoga, CA | Full-Time

Saratoga, California

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13d ago

We re looking for a seasoned DFT Leader to architect and drive test strategy for complex multi-chip SoCs at advanced nodes (7nm and below). Own DFT architecture (Scan, LBIST, MBIST, Memory Repair, OCC, ACJTAG/DCJTAG) Lead ATPG & achieve high @speed scan coverage Hands-on with Synopsys or Mentor test tools Multiple deep submicron tape-outs required SerDes + EMIB exposure is a plus 15+ years semiconductor experience This is a high-impact leadership role shaping next-gen high-performance silicon.

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Full-time

Depends on Experience

Principal DFT Engineer (Silicon Engineering)

Sunnyvale, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. PRINCIPAL DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world'

Full-time

USD 210,000.00 - 295,000.00 per year

CPU DFT Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a DFT Engineer you will work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design for Debug) architecture, implementation, and test plans for both mixed signal and digital VLSI designs. Then you'll insure it becomes reality. We're doing a ground up implementation of a new chip architecture, so you'll have to ab

Full-time

USD 142,200.00 - 213,400.00 per year

DFT Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most complex and cutting edge network switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, t

Full-time

USD 120,000.00 - 192,000.00 per year

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