DFT Engineer

DFT Engineer: QFocus / Meta

Location: Sunnyvale, CA
Rate: Up to $65/hr C2C
Duration: Long-term
Experience: 5-15 years (strong candidates only)

What you’ll do

• Define and implement DFT for SoCs/ASICs: scan, ATPG, MBIST, JTAG (IEEE 1149.1, 1500, 1687).
• Insert and optimize scan chains, and integrate MBIST with repair.
• Generate ATPG patterns (stuck-at, at-speed, cell-aware).
• Run gate-level and SDF simulations in Verilog/SystemVerilog.
• Run DFT lint and rule checks (SpyGlass, Tessent, Modus, TetraMAX).
• Convert patterns to tester formats (WGL, STIL) for ATE.
• Support post-silicon bring-up, debug first silicon, and help improve test time and yield.

Must have

• 3+ years of hands-on DFT on advanced SoC/ASIC nodes (the client’s range is 5-15).
• Verilog/SystemVerilog.
• Scan insertion, including compressed scan (EDT/SmartTest).
• ATPG and fault grading.
• MBIST insertion and repair.
• JTAG, including TAP controllers.
• Post-silicon pattern bring-up and yield support.

Nice to have

• Tcl, Python or Perl scripting.
• High-speed IO, SerDes loopback or analog DFT.
• Design Compiler or Genus, plus STA constraints for DFT modes.