
TekLeaders, Inc
Remote or San Francisco, California • Today
Easy Apply
Full-time, Part-time, Third Party, Contract
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TekLeaders, Inc
Remote or San Francisco, California • Today
Easy Apply
Full-time, Part-time, Third Party, Contract





Reliable Robotics
Remote or Mountain View, California • Today
Full-time
USD 215,000.00 - 300,000.00 per year

Reliable Robotics
Remote or Mountain View, California • Today
Full-time
USD 185,000.00 - 230,000.00 per year






Lockheed Martin Corporation
Remote or Colorado Springs, Colorado • Today
Full-time
USD 89,300.00 - 157,550.00 per year


Qualcomm Technologies
Remote or Santa Clara, California • Today
Full-time
USD 167,100.00 - 250,700.00 per year

Job Title : PCIe Verification Engineer
Job Location - Address : San Francisco, California, United States - remote
Client Interview : No
Study Level : Bachelor's Degree
Skill Cluster : 423 - DA-Platfrm Pega AccelQ.
Primary Skill : Simulator, C++
Experience : 12+ years
Job Description :
Job Description
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Cornelis Networks
San Francisco, California
•
Today
At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software development. We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale. At Cornelis we're building the future of AI and HPC networking with an AI-first approach to silicon and software developmen
Full-time
South San Francisco, California
•
Today
About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Job Description & Responsibilities: We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design and verification fundamentals to work in Neuralink's System-on-Chip (SoC) department under the Implant Team. This position offers
Full-time
USD 131,000.00 - 243,000.00 per year
Sunnyvale, California
•
17d ago
Key Responsibilities Pre-Silicon Develop and execute test plans for PCIe Gen3/Gen4/Gen5/Gen6 IP blocks and SoC-level integrationCreate directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionalityPerform protocol-level analysis using VIP (Verification IP) environments and bus functional modelsDebug RTL-level issues related to link training, power management (ASPM, L-states), equalization, and error handlingCollabora
Easy Apply
Contract
Depends on Experience
San Francisco, California
•
Today
At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and especially motivated Analog Mixed Signal IP Integration Engineer! As a member of our dynamic group, you will have the rare and great opportunity to work on upcoming products that will delight and encourage millions of Apple's customers every day! Description In this highly
Full-time