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Formal Verification Engineer - #26-21752

U.S. Tech Solutions Inc.

Ben Lomond, California • 12d ago

Easy Apply

Contract

$80 - $85

Senior Staff Formal Verification Applications Engineer

Synopsys, Inc.

Sunnyvale, California • Today

Full-time

CPU Formal Verification Engineer

Qualcomm

Santa Clara, California • Today

Full-time

Compensation information provided in the description

Formal Design Verification Engineer

NUBYT, INC.

San Jose, California • 2d ago

Easy Apply

Contract, Third Party

85 - 95

Senior Staff Formal Verification Engineer

J VERS LLC

San Diego, California • Today

Full-time

USD 195,200.00 - 325,000.00 per year

GPU Formal Verification Engineer

Apple, Inc.

Santa Clara, California • Today

Full-time

CPU Formal Verification Engineer

Qualcomm Technologies

Santa Clara, California • Today

Full-time

USD 147,900.00 - 221,900.00 per year

Staff Applications Engineer, Synthesis and Formal Verification

Synopsys, Inc.

Sunnyvale, California • Today

Full-time

Pre-Silicon Digital Verification Engineer

Apple, Inc.

Sunnyvale, California • Today

Full-time

Low-Power & CDC Verification Engineer

AMD (Advanced Micro Devices)

Santa Clara, California • Today

Full-time

USD 103,600.00 per year

Senior Debug Verification Engineer

Altera Corp.

San Jose, California • Today

Full-time

USD 149,100.00 - 215,000.00 per year

Engineer - Processor Verification and Compiler Validation

Enphase Energy

Fremont, California • Today

Full-time

USD 85,000.00 - 129,000.00 per year

Sr. Staff Engineer - Processor Verification and Compiler Validation

Enphase Energy

Fremont, California • Today

Full-time

USD 135,000.00 - 205,200.00 per year

Senior Staff Pre Silicon Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

ASIC Verification Engineer

Cornelis Networks

San Jose, California • Today

Full-time

Lead ASIC Verification Engineer

General Dynamics

Remote or Boise, Idaho • Today

Full-time

USD 173,032.00 - 190,000.00 per year

Principal Application Engineer - Verification

Synopsys, Inc.

California • Today

Full-time

Advanced ASIC FPGA Verification Engineer (Sign-on Bonus Available)

General Dynamics

Remote • Today

Full-time

USD 122,785.00 - 136,215.00 per year

Lead ASIC Verification Engineer

System One

Hybrid in San Jose, California • Today

Easy Apply

Contract

75 - 85

Principal Verification Engineer

CesiumAstro

Aliso Viejo, California • Today

Full-time

USD 165,000.00 - 199,000.00 per year

Specialist, Systems Engineer - Verification and Test

Harris Corporation

Los Angeles, California • Today

Full-time

USD 92,500.00 - 171,500.00 per year

FPGA Verification Engineer II

CesiumAstro

El Segundo, California • Today

Full-time

USD 118,000.00 - 142,000.00 per year

Digital Verification Engineer

Neuralink

South San Francisco, California • Today

Full-time

USD 131,000.00 - 243,000.00 per year

Senior Verification & Simulation Product Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 143,500.00 per year

Senior Staff Engineer, GPU Design Verification (Subsystems)

Samsung Electronics America

San Jose, California • Today

Full-time

USD 180,200.00 - 297,200.00 per year

Principal Engineer, Digital Verification and Emulation

Ayar Labs

San Jose, California • Today

Full-time

USD 190,000.00 - 250,000.00 per year

Principal SerDes Bring-up Validation Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 185,000.00 - 240,000.00 per year

System Verification and Validation Engineer- Multi-Technology Product Test

Schneider Electric

Lake Forest, California • Today

Full-time

USD 101,600.00 - 152,400.00 per year

SOC Verification and Methodology Engineer

Qualcomm Technologies

San Diego, California • Today

Full-time

USD 174,400.00 - 261,600.00 per year

Senior Staff Engineer, GPU Design Verification (Formal Verification)

Samsung Electronics America

San Jose, California • Today

Full-time

USD 198,200.00 - 297,200.00 per year

Job Details

Skills

VERIFICATION
UVM
VERILOG
SYSTEMVERILOG

Summary

Duration: 12+ Months

Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
Be familiar with hardware modeling and/or assertion-based verification methods.

EXPERIENCE AND EDUCATION:

5-7 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting.
Strong background in C/C++ development in a Linux Environment.
Strong debug skills and experience with debug tools such as Gdb, Valgrind.
Proficient in Object Oriented programming, STL, computer architecture and data structures.
Knowledge of Perl and Makefiles.
Experience in Verilog/SystemVerilog/SystemC, preferred.
Experience in C/Verilog environment using DPI/PLI, preferred.
Strong analytical skills and attention to detail.
Excellent written and communication skills.

About US Tech Solutions:
US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit .

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

AI Statement: By applying, you acknowledge that AI-assisted tools may be used during hiring.

#LI-AS140

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: usts
Position Id: 26-21752
Posted 12 days ago

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RTL Verification Engineer # 26-21738

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Duration: 12+ Months About the role:Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-ra

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Job Description JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random t

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Verification Engineer ASIC/CPU/GPU Functional Verification

San Jose, California

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We are looking for a highly experienced ASIC Verification Engineer to support functional verification activities for complex ASICs and IP cores as part of a next-generation CPU/GPU development program. The ideal candidate will have strong experience in hardware verification, C/C++ development, Linux environments, and debugging complex systems. You will collaborate closely with design and verification teams to understand design specifications, develop test plans, execute functional tests, and ens

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Verification Engineer 4 - 1 - San Jose Experience - 8-10 Years preferable JOB DUTIES: Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system. Be responsible for carefully documenting and executing tes

Easy Apply

Contract, Third Party

Depends on Experience

Job Details

Skills

VERIFICATION
UVM
VERILOG
SYSTEMVERILOG

Summary

Duration: 12+ Months

Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.
Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.
Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.
Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.
Be familiar with hardware modeling and/or assertion-based verification methods.

EXPERIENCE AND EDUCATION:

5-7 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting.
Strong background in C/C++ development in a Linux Environment.
Strong debug skills and experience with debug tools such as Gdb, Valgrind.
Proficient in Object Oriented programming, STL, computer architecture and data structures.
Knowledge of Perl and Makefiles.
Experience in Verilog/SystemVerilog/SystemC, preferred.
Experience in C/Verilog environment using DPI/PLI, preferred.
Strong analytical skills and attention to detail.
Excellent written and communication skills.

Dice Id: usts
Position Id: 26-21752
Posted 12 days ago

Fitment

Dice Job Match Score™

To see how well you match this job, please log in or create an account.

Once logged in, be sure to complete your profile to get the most accurate match score.

Create job alert

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Similar Jobs

RTL Verification Engineer # 26-21738

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