Physical Design Engineer

Role: Physical Design Engineer
Client: Broadcom
Employment Type: Full-Time
Locations: San Jose, CA / San Diego, CA / Irvine, CA
Experience: 12+ Years
Salary Range: $130,000 - $190,000 per annum


Key Responsibilities

Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure activities.
Setup and synthesize RTL designs.
Perform timing closure using various methodologies and strategies, including top-level STA.
Conduct EM/IR analysis.
Execute Place & Route (P&R).
Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.
Perform floorplanning and layout activities, preferably with top-level floorplanning expertise.
Contribute to flow and methodology development.
Collaborate closely with IC Design and RTL Engineering teams.


Required Skills

Strong experience with Cadence Innovus.
Expertise in the complete Physical Design cycle from RTL to Tape-out.
Hands-on experience in:
Synthesis
Static Timing Analysis (STA)
Timing Closure
Place & Route
Clock Tree Synthesis (CTS)
Floorplanning
Physical Verification
EM/IR Analysis
Strong TCL and/or PERL scripting skills.
Proficiency with industry-standard EDA tools.
Excellent communication and collaboration skills.


Education

Bachelor's Degree in Electrical Engineering, Electronics Engineering, or related field.


Preferred Profile

Deep expertise in top-level floorplanning and STA.
Proven success delivering complex ASIC/SoC designs through tape-out.


Please share qualified candidates with updated resumes, current location, work authorization status, expected salary, and availability.