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Skills

Integrated Circuit
RTL
Meta-data Management
Analytics
Optimization
Artificial Intelligence
Regression Analysis
Database
Collaboration
Debugging
Evaluation
Electrical Engineering
Computer Science
Engineering Design
Semiconductors
Python
Shell
Tcl
Perl
Machine Learning (ML)
Workflow
Place And Route
Layout
LVS
Static Timing Analysis
Change Data Capture
DFT
Data Analysis
EDA

Summary

Description

Position Overview:

Work closely with design teams and CAD/EDA stakeholders to identify workflow bottlenecks across the chip development lifecycle-such as DRC/CDC/STA debug, regression triage, PPA convergence, and ECO iteration. This role focuses on building scalable data pipelines and models, and integrating AI-driven solutions into production CAD and verification flows.

Responsibilities:

Identify and prioritize high-impact opportunities to apply AI/ML to chip design and verification workflows, spanning RTL-to-GDS, signoff, debug, and regression
Build and maintain data pipelines to extract, normalize, and analyze signals from EDA tool logs, reports, run artifacts, and design metadata (e.g., timing reports, violations, coverage, failures)
Develop ML models, heuristics, and analytics to improve efficiency and quality in areas such as STA, DRC/LVS, ECO optimization, and debug acceleration
Integrate AI solutions into existing CAD infrastructure, including automation systems, regression frameworks, job schedulers, and design databases
Collaborate with EDA vendors as needed for tool enablement, feature requests, debugging, and evaluation of vendor solutions versus internal implementations

Requirements:

BS or MS in Electrical Engineering, Computer Science, or equivalent industry experience
2+ years of experience in CAD/EDA flow engineering, design automation, or a related semiconductor workflow role
Strong programming skills, with Python required; experience with shell, Tcl, or Perl as needed
Hands-on experience applying machine learning to real-world engineering problems
Solid understanding of at least one major EDA workflow domain (e.g., place & route, physical layout, DRC/LVS, STA, power, CDC, DFT, simulation/regressions)
Experience working with large-scale, noisy operational data (EDA logs and reports) and building robust automation around it

Annual base salary for this role in California, US is expected to be between $110,000 - $145,000. Actual pay will be determined by several factors such as relevant skills and experience, and the pay of employees in a similar role.

EOE/Minorities/Females/Vet/Disability

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10119130
Position Id: 3b2420c8eaa2d2a60fcd8259892907db
Posted 30+ days ago

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Sr. EDA Flow Engineer

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