Never miss an opportunity! Create an alert based on the job you applied for.San Jose, California
•
Today
We are seeking an experienced Senior Design Verification (DV) Engineer with expertise in SoC/IP verification, SystemVerilog/UVM, and modern verification methodologies. The ideal candidate will lead end-to-end verification activities for IP, Subsystem, and SoC-level designs while collaborating with design, architecture, and cross-functional teams to achieve verification closure.Key ResponsibilitiesDevelop and execute verification plans for IP, Subsystem, and SoC-level designs.Verify SoCs with ARM
Easy Apply
Third Party, Contract
Depends on Experience