Onsite || DV Engineer || San Jose CA

We are seeking an experienced Senior Design Verification (DV) Engineer with expertise in SoC/IP verification, SystemVerilog/UVM, and modern verification methodologies. The ideal candidate will lead end-to-end verification activities for IP, Subsystem, and SoC-level designs while collaborating with design, architecture, and cross-functional teams to achieve verification closure.Key ResponsibilitiesDevelop and execute verification plans for IP, Subsystem, and SoC-level designs.Verify SoCs with ARM

Job Title: Senior Design Verification EngineerLocation: San Jose, CA(Onsite)Position Type: Contract Job Description:The Senior Engineer DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves technical ownership and close collaboration with design, architecture, and customer teams to achieve verification closure with high quality. Key Responsibilities:Design Verification of SOCs with embedded ARM CPUs, DSP

Job Description:The Senior Engineer DV is responsible for leading and executing end-to-end design verification activities for IP, Subsystem, or SoC-level projects. This role involves technical ownership and close collaboration with design, architecture, and customer teams to achieve verification closure with high quality.Key ResponsibilitiesDesign Verification of SOCs with embedded ARM CPUs, DSPs, DDR3, peripherals and interconnect protocols such as AHB, AXI, PCI Express etc.Strong in HVL (UVM