Sr. Design Verification Engineer

Role: Senior Design Verification Engineer 
Location: San Jose, CA (Onsite)
Experience: 7+ Years 

What candidate will Be Doing: 

• Strong expertise along with complex SoC/IP debug is a must
• At-least 5+ years of experience in System Verilog HVL and C/C++.
• AMBA AXI bus along-with ARM or C based processor
• Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench,
• stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. 

What we are looking for: 

• Low Power Verification in UPF/net-list Simulation good to have
• Make/Perl/Python
• Ensure customer satisfaction.
• Reporting to customers on daily or weekly progress effectively