Design Verification (DV) Lead

Hello Sir , Position : Design Verification (DV) Lead (Managerial level )Location : Sunnyvale, CA, USA OnsiteEmployment Type : Full Time What You will Do:Develop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root-cause and resolve functional failures in the design, partnering with the design/arch teamCollaborate with cross-functional teams like Design, Model, Emulation a

We are seeking an experienced Senior Design Verification (DV) Engineer with expertise in SoC/IP verification, SystemVerilog/UVM, and modern verification methodologies. The ideal candidate will lead end-to-end verification activities for IP, Subsystem, and SoC-level designs while collaborating with design, architecture, and cross-functional teams to achieve verification closure.Key ResponsibilitiesDevelop and execute verification plans for IP, Subsystem, and SoC-level designs.Verify SoCs with ARM

We have opening for Design Verification Engineer, Principal Location - Santa Clara, CA Full time permanent position Sponsorship available Must-haves BS Computer Engineering, Electrical Engineering, or Computer Science 10+ years of verification and firmware and software development experience (or MS/PhD 5+ years experience). Proven track records of leading Design Verification implementation activity Tape-out of complex SOC under tight schedule. In depth understanding and experience with System V

Job Title: Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle. Key Skills Required 8+ years of Design Verification experience in s