REQ: STA Engineer in San Jose, CA.

Position: Static Timing Analysis Engineer Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do: Develop and validate timing constraints for intricate SoC designs. Expertise in Synthesis, Equivalency Checking and STA. Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus. Experience with Synopsys Tools Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA. Define and im