REQ: STA Engineer in San Jose, CA.

Position: Static Timing Analysis Engineer Locations: San Jose, San Diego, Irvine, CA (Onsite) What You Will Do: Develop and validate timing constraints for intricate SoC designs. Expertise in Synthesis, Equivalency Checking and STA. Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus. Experience with Synopsys Tools Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA. Define and im

Company:Qualcomm Atheros, Inc. Job Area:Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm-Atheros, a.k.a. QCA is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role involves ownership and leading Static timing closure and synthesis for complex low-power WiFi SoCs and sub-systems.

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. As CPU STA CAD engineer, you will build and su

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience) Location: San Jose, CA (Onsite role) Type: FTE Permanent role Note from Hiring manager: Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered. Only in those cases where y