Mixed Signal Verification Engineer _San Jose, CA (Onsite, Only local Candidates)

Job Title: "Mixed Signal Verification Engineer" Location: San Jose, CA (Onsite) Duration: Long Term Contract JOB RESPONSIBILITIES Creating AMS/DMS testbench for wireless RF and High Speed PHY. Working with RF/Analog design engineers for analog circuit models Support silicon bring-up and commercialization. REQUIRED SKILLS BS or BE minimum, 3+ year experiences Deep understanding of digital VLSI simulation flow Deep understanding of mixed-mode and analog simulation flow Experience with Verilog/Sys

//NOTE- NEED ONLY LOCAL CANDIDATE TO SAN JOSE, CA Role - Software Engineer (AI Agent Platform) Location - San Jose, CA (Onsite) Client - Confidential Rate - $90 Interview Mode - Face to Face Duration - 12+ Months (Possibility of extension) Build and enhance an internal AI agent platform that empowers Cisco employees to interact with enterprise knowledge through conversational interfaces (Webex, web). Design and develop multi-agent workflows powered by Large Language Models (LLMs) to automate kn

[ Only Xoriant W2, No Vendor Candidates] Title: Cellular PHY Layer Software Engineer | 5G Modem Systems Location: San Jose, CA (Onsite) Duration: 6+ Months (Possible Extension) Interview Mode: onsite Rate: $85/hr on W2 (No Benefits) Job Summary We are seeking a highly motivated Modem Software Engineer with strong expertise in cellular technologies, embedded systems, and L1/PHY layer development. In this role, you will contribute to the development, optimization, and commercialization of next-gen

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. TITLE:- Sr. Staff Engineer (SystemVerilog & Digital Verification)LOCATION:- SanJose, CA (onsite)This role is part of a large RFC/RFIC/DFT engineering organization, focused on advanced digital verification across complex SoC and mixed-sig