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Sr. Design Verification Engineer || San Jose, CA

McKinsol Consulting Inc

San Jose, California • Today

Easy Apply

Contract, Third Party

Depends on Experience

ASIC/FPGA Design and Verification Engineer - Space Electronics - (Senior or Principal) - MTV

Boeing Company

Mountain View, California • Today

Full-time

USD 164,900.00 - 223,100.00 per year

Senior Staff Engineer, GPU Design Verification (Subsystems)

Samsung Electronics America

San Jose, California • Today

Full-time

USD 180,200.00 - 297,200.00 per year

Sr. ASIC/SoC Design verification Engineer

Mavensoft Technologies, LLC

Remote • 6d ago

Easy Apply

Contract

120 - 127

Senior Staff Pre Silicon Verification Engineer

AMD (Advanced Micro Devices)

San Jose, California • Today

Full-time

USD 175,000.00 per year

Senior System Validation Engineer

OSI Engineering, Inc.

Hybrid in Sunnyvale, California • Today

Easy Apply

Contract

Depends on Experience

Senior ASIC Verification Engineer

Cornelis Networks

San Jose, California • Today

Full-time

ASIC/FPGA Design and Verification Engineer - Space Electronics - MTV (Associate, Experienced, or Lead)

Boeing Company

Mountain View, California • Today

Full-time

USD 98,600.00 - 133,400.00 per year

Senior Debug Verification Engineer

Altera Corp.

San Jose, California • Today

Full-time

USD 149,100.00 - 215,000.00 per year

Sr Principal Mixed Signal Verification Engineer

Qorvo, Inc.

San Jose, California • Today

Full-time

USD 193,100.00 - 251,100.00 per year

Senior Performance Verification Engineer - SoC

Microsoft Corporation

Mountain View, California • Today

Full-time

USD 119,800.00 - 234,700.00 per year

Sr. FPGA Verification Engineer

Reliable Robotics

Remote or Mountain View, California • Today

Full-time

USD 215,000.00 - 300,000.00 per year

Senior System Level Verification Engineer

Axiado

San Jose, California • Today

Full-time

Sr. Staff CAD- ASIC Design Verification Agentic Workflow

Marvell Semiconductor Inc.

Santa Clara, California • Today

Full-time

USD 127,630.00 - 191,200.00 per year

Sr. Staff Validation Engineer

Marvell Semiconductor Inc.

Santa Clara, California • Today

Full-time

USD 127,630.00 - 191,200.00 per year

Sr. Principal Software Engineer, Physical Verification

Cadence Design Systems Inc

San Jose, California • Today

Full-time

USD 161,000.00 - 299,000.00 per year

Sr. Staff Engineer - Processor Verification and Compiler Validation

Enphase Energy

Fremont, California • Today

Full-time

USD 135,000.00 - 205,200.00 per year

Senior DevOps Validation Engineer

Keeper Security, Inc.

Remote • Today

Full-time

Senior Director, Design Engineering

Celestica International LP

San Jose, California • Today

Full-time

USD 208,000.00 - 367,000.00 per year

Sr. FPGA Verification Engineer, Radar

Reliable Robotics

Remote or Seattle, Washington • Today

Full-time

USD 215,000.00 - 300,000.00 per year

Senior Staff Engineer, GPU Design Verification (Formal Verification)

Samsung Electronics America

San Jose, California • Today

Full-time

USD 198,200.00 - 297,200.00 per year

Senior Engineer, Process Validation

Danaher Corporation

Remote • Today

Full-time

USD 100,000.00 - 130,000.00 per year

Senior Hardware Validation Engineer

Wing

Palo Alto, California • Today

Full-time

USD 211,000.00 - 224,000.00 per year

Infinity Fabric Senior Staff Pre-Si Verification Engineer

AMD (Advanced Micro Devices)

Santa Clara, California • Today

Full-time

USD 175,000.00 per year

Senior Director System Validation Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 240,000.00 per year

Senior SoC Verification/Validation Engineer

Astera Labs

San Jose, California • Today

Full-time

USD 165,000.00 per year

Senior Software Design Assurance (Sr Software Design Quality) Engineer

Dexcom

Remote • Today

Full-time

USD 95,900.00 - 159,900.00 per year

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX

Palo Alto, California • Today

Full-time

USD 175,000.00 - 280,000.00 per year

Senior Staff Engineer, Design Verification

Samsung Electronics America

San Jose, California • Today

Full-time

USD 189,000.00 - 301,000.00 per year

Senior RTL Design Engineer Networking ASIC / SystemVerilog / Ethernet San Diego

Sivaltech

San Jose, California • 2d ago

Easy Apply

Third Party, Contract

Depends on Experience

Job Details

Skills

Interfaces
Emulation
Ethernet
IPS
Integrated Circuit
Intellectual Property
PCI Express
AMBA
ARM
AXI
Regulatory Compliance
System On A Chip
SystemVerilog
CPU
Collaboration
Computer Hardware
DV
IP
RTL
Startups
UVM

Summary

Sr. Design Verification Engineer
Location: San Jose, CA ( Onsite )

Facet to face interview is a must after Video call.

Job Summary

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key responsibilities

End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
Understand vendor IP configurations and handle handshake with internal IP team
Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

You may be a good fit if you have

8+ years of design verification experience
You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.
You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.
You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.
You collaborate naturally with cross-functional teams from RTL design to software and emulation and can clearly communicate technical insights.

Strong candidates may also have experience with

Experience handling vendors and integration of IP/VIP s
UVM/System Verilog

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10299481
Position Id: 9116418
Posted 10 hours ago

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Contact the job poster

Sachin Agrawal

IT Recruiter @ McKinsol Consulting Inc

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San Jose, California

•

Yesterday

Role: Design Verification Engineer IP / SoC Verification Location: San Jose, Bay Area, CA Work Mode: 100% Onsite Job Type: Contract Candidate Preference: Local candidates only We are looking for an experienced Design Verification Engineer to join the Interface IP Design Verification team. The ideal candidate will have strong hands-on expertise in SystemVerilog, UVM, IP-level verification, and protocol validation. Key Responsibilities Own end-to-end verification of IP subsystems such as PCIe, Et

Easy Apply

Contract

Depends on Experience

Design Verification Engineer

San Jose, California

•

Today

NMK Global Inc.is a global IT Services & Solutions company specializing in IT Staffing, Technology Consulting, Workforce Solutions, and Application Development Services. We help organizations build high-performing technology teams by connecting them with exceptional talent across a wide range of industries. Our expertise, industry knowledge, and consultative approach enable clients to achieve successful business outcomes while helping professionals advance their careers. Job Title: Design Ver

Easy Apply

Contract, Third Party

Depends on Experience

Design Verification Engineer – UVM/SystemVerilog

San Jose, California

•

2d ago

Job SummaryWe are seeking an experienced Design Verification (DV) Engineer to join our Interface IP Design Verification team. The ideal candidate will have strong hands-on experience in SystemVerilog and UVM-based verification, along with expertise in validating complex IP subsystems and standard interface protocols. You will collaborate closely with architects, RTL designers, integration teams, and external IP vendors to ensure functional correctness, performance, and compliance with architectu

Easy Apply

Contract

Depends on Experience

Design Verification Engineer

San Jose, California

•

Today

Location : Bay area (San Jose) CA Onsite Duration : Long term Locals We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges

Easy Apply

Contract

Depends on Experience