Role: Design Verification Engineer – IP / SoC Verification
Location: San Jose, Bay Area, CA
Work Mode: 100% Onsite
Job Type: Contract
Candidate Preference: Local candidates only
We are looking for an experienced Design Verification Engineer to join the Interface IP Design Verification team. The ideal candidate will have strong hands-on expertise in SystemVerilog, UVM, IP-level verification, and protocol validation.
Key Responsibilities
✅ Own end-to-end verification of IP subsystems such as PCIe, Ethernet, ARM/ARC CPU, low-power peripherals, and sensors.
✅ Develop and maintain scalable, reusable UVM/SystemVerilog-based verification environments.
✅ Understand vendor IP configurations and coordinate with internal IP teams and external vendors.
✅ Verify functional correctness, performance, and compliance with IP specifications.
✅ Collaborate with RTL design, SoC integration, and system verification teams.
✅ Drive functional coverage closure, debug complex issues, and support verification sign-off.
✅ Develop test scenarios covering corner cases, stress conditions, and protocol requirements.
Required Skills
🔹 8+ years of Design Verification experience
🔹 Strong hands-on experience with SystemVerilog and UVM
🔹 Experience in IP subsystem verification and reusable testbench development
🔹 Knowledge of interface protocols such as PCIe, Ethernet, AXI/AMBA
🔹 Experience with IP integration, verification coverage, and sign-off
🔹 Strong debugging, problem-solving, and cross-functional collaboration skills
🔹 Ability to work independently in a fast-paced engineering environment
Nice to Have:
⭐ Vendor IP / VIP integration experience
⭐ ARM/ARC CPU verification
⭐ Low-power peripheral or sensor IP verification
⭐ SoC-level integration and hardware-software validation experience
