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Job Title: Design Verification Engineer III
Location: Sunnyvale, CA (Onsite 3 days/week)
Duration: Contract - 6 months, extension TBD
Pay Range: $60/hr - $65.32/hr (W2).
Job ID: 407927
About BCforward
BCforward is a leading global IT consulting and workforce solutions firm providing services and support to Fortune 500 and government clients. Founded in 1998, BCforward has grown with our customers needs into a full-service business solutions provider. With delivery centers and offices across North America and India, we take pride in building long-term relationships and delivering excellence through innovation, collaboration, and integrity.
Job Description
We are seeking a Design Verification Engineer to join our dynamic team. The ideal candidate will have strong experience in SystemVerilog/UVM, coverage-driven verification, RTL debug, and power/performance measurement and a proven ability to build scalable verification environments, achieve coverage closure, and deliver high-quality silicon IP verification outcomes.
Responsibilities:
- Develop and execute verification plans for RTL blocks/IPs across the subsystem.
- Build and maintain SystemVerilog/UVM testbenches and write directed and constrained-random tests.
- Drive functional coverage and assertion (SVA) closure and run and triage regressions.
- Measure power and performance across design stages using PPA RTL and PrimeTime PX (or equivalent) and correlate with post-silicon data to inform design and power modeling teams.
- Build dashboards for power and performance tracking and publishing.
- Debug RTL failures using waveform analysis and Verdi and provide actionable feedback to design and verification teams.
- Contribute to automation of verification, regression, and power/performance measurement flows using Python.
Required Skills & Qualifications:
- Proven SystemVerilog and UVM verification experience, including testbench architecture, sequences, drivers, and monitors.
- Functional coverage, constrained-random, and assertion-based verification (SVA) with demonstrated coverage closure.
- Strong RTL debug with industry simulators such as VCS, Xcelium, or Questa and waveform tools such as Verdi.
- Working knowledge of RTL design principles and digital design fundamentals.
- Proficiency in Python or Perl scripting for automation.
Preferred Skills:
- Experience with power measurement tools such as PrimeTime PX (PTPX) or PrimePower.
- Low-power and power-aware verification using UPF and power-aware simulation in advanced nodes at or below 7nm.
- Formal verification and/or emulation experience with platforms such as Palladium or Zebu.
- Familiarity with the RTL-to-GDSII flow.
- Data analysis or ML approaches for coverage analysis or debug triage.
Education:
BS in Electrical Engineering, Computer Engineering, or Computer Science required. MS preferred but not required.
Top 3 Must-Have Skills:
- SystemVerilog and UVM testbench development.
- Functional coverage and assertion-based verification with coverage closure.
- RTL debug with VCS or Xcelium and Python-based automation, including power and performance measurement.
Day-to-Day Overview:
Build and run testbenches and regressions, analyze coverage, debug failures, and measure power and performance in collaboration with the design team. Work daily with a small team of two to three teammates and other contingent workers. Emphasis is on front-end DV focused on RTL verification.
Recruiter Keywords / Related Titles:
Design verification, DV engineer, SystemVerilog, UVM, functional coverage, ASIC verification, RTL verification, low-power verification, power measurement, PTPX.
Why BCforward?
At BCforward, we believe in advancing lives and careers. When you join our team, you gain access to:
- Competitive compensation and benefits.
- Opportunities for growth with global clients.
- A supportive, inclusive culture that values innovation and people.
- Exposure to cutting-edge technologies and projects.
About Our Commitment
BCforward is an equal opportunity employer. We value diversity and are committed to creating an inclusive environment for all employees. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, gender identity, national origin, age, disability, or veteran status.
Fair Chance Notice (CA):
Pursuant to applicable California and local Fair Chance laws and ordinances, qualified applicants will be considered for assignment with arrest and conviction records, subject to a job-related assessment of the duties and requirements described above.
Interested? Apply Now!
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