Lead Architecture & Performance Modeling Engineer
Full Time opportunity in Saratoga, CA.
We are seeking a highly skilled and visionary Lead Performance Modeling Engineer to drive the definition, development, and application of architectural and performance modeling infrastructure. In this role, you will set the direction for modeling efforts that directly influence our ASIC architecture and microarchitecture (uArch) designs. You will collaborate closely with system architects, chip designers, and cross-functional teams to evaluate design trade-offs, identify bottlenecks, and deliver actionable insights that shape the future of large-scale AI networking. This is an opportunity to establish a modeling strategy at the cutting edge of AI hardware while working alongside a team of talented performance engineers.
Responsibilities
Lead the development and deployment of high-level performance models for networking devices to guide architectural decisions.
Define modeling methodologies and frameworks that ensure consistency, accuracy, and scalability across projects.
Partner closely with ASIC architects and uArch teams to evaluate trade-offs in throughput, latency, power, and area.
Drive performance analysis and bottleneck identification to inform and influence architecture and design choices.
Oversee the creation and validation of structural and traffic models to explore real-world workloads and system scenarios.
Establish and champion best practices for performance modeling, documentation, and reporting.
Qualifications
MSEE/PhD in Electrical Engineering, Computer Engineering, or a related field with 10+ years of relevant industry experience.
Proven track record of technical leadership in performance modeling or architecture for ASICs, SoCs, or networking systems.
Deep expertise in networking protocols such as Ethernet and PCIe.
Proficiency in modeling languages and tools, including C, C++, Python, and scripting environments.
Strong background in FPGA/ASIC design flows, including synthesis, simulation, and verification tools (e.g., Verilog, VHDL, Synopsys, Cadence).
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