About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your ImpactThe Data Center Engineering (DCE) team at Marvell is seeking candidates for a Senior Staff Static Timing Analysis (STA) engineering position. Common projects within DCE range from artificial intelligence and machine learning, to wired and wireless infrastructure, with the latest technology nodes. The team utilizes the latest EDA software tools, and work through the technical challenges to insure we meet the performance, power, and area requirements of the design. This position will work in tandem with the Physical Design, Design For Test, and other teams both at a local and global level.
This role will be located in Morrisville, NC
What You Can Expect- In this full time in office role at this site, you will be a Timing Sub-System/Partition Lead, responsible for timing closure at your hierarchical level, and all blocks within
- Work with design teams across various disciplines such as DFT, RTL, and IP in the process of iterative timing feedback and closure
- Deliver to the SoC level all necessary collateral of your sub-system/partition per the required schedule
- Conduct and adjust timing correlation between PD tools and signoff, along with participating in early feasibility studies
- Provide pushdown timing ECOs to blocks within the sub-system/partition
- Work closely with the block level PD engineers in debugging and resolving timing issues at their level, but also interface timing at the sub-system/partition level
- Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
- Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation
- Responsible for managing tool independent timing constraints that will work for synthesis, place & route and static timing analysis
What We're Looking ForMinimum Qualifications - BS in EE/CE/CS with 5+ years of experience, or MS in EE/CE/CS with 3+ years of experience
- 3 years practical experience in Timing Analysis and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
- Worked in the latest technology nodes, and experience in advanced timing concepts such as SI, CDC, LVF, POCV, and MIS
- Good understanding of Verilog/VHDL, along with general digital logic and architecture
- Proficient at running sub-system (ie. partition) level timing signoff
- Proficient in UNIX, and shell based scripting
- Knowledge and Experience in both TCL and Python languages
- Have some proficiency in Synthesis and Physical Design
- Diligent, detail-oriented, and able to handle assignments with minimal supervision
- Must possess good communication skills, be a self-driven individual and a good team player
- Familiar and experienced with the balancing the trade-offs of Performance, Power, and Area
Preferred Qualifications (in addition to the minimum qualifications) - BS in EE/CE/CS with 10+ years of experience, or MS in EE/CE/CS with 5+ years of experience
- 5 years practical experience in Timing Analysis and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
- Leading timing closure effort with a small team of engineers
- Practical experience with Synopsys Timing Tools, such as Primetime and Tweaker
- Experience in timing methodology and flow development
Expected Base Pay Range (USD)125,900 - 186,260, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at
Interview IntegrityAs part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews. Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.#LI-VM1
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